移位時鐘 的英文怎麼說

中文拼音 [yíwèishízhōng]
移位時鐘 英文
shift clock
  • 移 : Ⅰ動詞1. （移動） move; remove; shift 2. （改變; 變動） change; alter Ⅱ名詞（姓氏） a surname
  • 位 : Ⅰ名詞1 （所在或所佔的地方） place; location 2 （職位; 地位） position; post; status 3 （特指皇帝...
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 移位 : bit shift
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. As object lessons to explain : 1 the nature and habits of oviparous animals, the possibility of aerial flight, certain abnormalities of vision, the secular process of imbalsamation : 2 the principle of the pendulum, exemplified in bob, wheelgear and regulator, the translation in terms of human or social regulation of the various positions clockwise of movable indicators on an unmoving dial, the exactitude of the recurrence per hour of an instant in each hour, when the longer and the shorter indicator were at the same angle of inclination, videlicet, 5 5 11 minutes past each hour per hour in arithmetical progression

    他把它們作為實物教材，用以說明： 1卵生動物的本性與習性，空中飛行的可能性，一種異常的視覺器官，世俗界用防腐藥物保存屍體的方式。 2體現于擺錘輪與整時器上的鐘擺的原理不動的針盤上那可移動的正轉的長短指針在各個位置作為人或社會規范所包含的意義長針和短針每小時在同一傾斜度相遇的那一瞬間，也就是說，按照算術級數，每小時超過5 5 11分的那一瞬間，每小時重復一次的精確性146 。
  2. To eliminate the bootless power dissipation of the redundant transition of the clock, a design method named det ( double - edge - triggered ) shift register is proposed

    摘要從消除時鐘信號冗餘跳變而致的無效功耗的要求出發，提出雙邊沿移位寄存器的設計思想。
  3. Then, we propose a design method named det ( double - edge - triggered ) shift register to eliminate the bootless power dissipation of the redundant transition of the clock

    接著，從消除時鐘信號冗餘跳變而致的無效功耗的要求出發，提出雙邊沿移位寄存器的設計思想。
  4. The third, the whole circuit of digital cmos image sensor is presented. the circuits of pixel array, clock signal generator and sam have been improved on the base of simulation

    再次，我們對整個cmos數字圖像傳感器進行了電路設計，主要包括：時鐘信號發生器，順序移位寄存器和像素陣列。
  5. Bits supplies the synchronous timing signal to these equipments inside the telecommunicationt building, such as dps, atm, no. 7, dxc, tm & adm in sdh, don and in etc. the related techniques are involved in the content of synchronization ne twork, timing distribution, the timing signal transportations x impairments etc. the second chapter tells the structure and the function of the building integrated timing system. the third chapter summarizes the digital synchronization network techniques, which emphasizes the basic concept of synchronization networks analyzes the necessity of building the synchronization network and introduces all kinds of synchronization methods. the fourth chapter represents the transportation of the synchronization signal

    本文第二章講述了通信樓綜合定時系統的構成及作用：第三章概述了數字同步網技術，著重描述了同步網的基本概念，分析了建立同步網的必要性，講述了各種同步方法；第四章闡述了同步定時信號的傳輸；第五章介紹了bits設備所支持的同步狀態消息；第六章、第七章為本文的重點，通過對時鐘信號建立數學模型，從理論上分析時鐘內部噪聲和相位瞬變產生時鐘定時信號損傷的原理，企圖尋找到更好地控制頻率漂移的方法。
  6. Readiness 1 point ability, requires deterrance replaces counterattack, ca is moved to the left 10 min cooldown ” when activated this ability immediately finishes the cooldown on your other hunter abilities

    預備（ 1點）需要： 1點威懾前置（替代原反擊位置，反擊被單獨移置預備左側）需要： 20點生存系天賦10分鐘冷卻時間激活后立刻使其他所有獵人技能冷卻。
  7. Aiming at the scheme of the signal electromagnetic environment simulator of the wireless communication system, the mission of this project is to design and realize twenty - four frequency synthesizers, which must meet high expectation for the phase noise characteristic and the spurious repression characteristic of the output clock signal. these frequency synthesizers provide the moving of the basic signal generating modules to radio frequency with stable inspiring source

    本課題的任務是針對通信信號電磁環境模擬器系統的方案要求，設計實現24個（頻率分佈在260mhz 1430mhz之間）對輸出時鐘信號的相位噪聲特性、雜散抑制特性等要求都很高的頻率合成器，為基本信號生成模塊到射頻的搬移提供穩定可靠的激勵源。
  8. Error : vhdl error at shift. vhd ( 18 ) : can ' t infer register for signal " q [ 3 ] " because signal does not hold its value outside clock edge

    每個時鐘上升沿移位一次，按您說的要加循環吧.移位一次沒問題，加上循環就不行了，有錯誤
  9. Although ranging is adopted, certain phase shifts still exist between bit flows from onus to olts. therefore, fast synchronization must be applied to synchronize the receiving clock of olt to the bit flow being received from a certain onu

    雖然採用了測距技術，但是各onu到達olt處的比特流仍存在一定的相位漂移，所以必須採取快速同步的技術，將olt的接收時鐘同步到當前所接收的、來自某一onu的比特流。
  10. The software can work successfully under 50mhz clock in simulation. at last this thesis gives some advices about the design of the oled ' s structure and the debugging scheme of the oled ' s driver

    綜合交流驅動和灰度移位調制輸出的設計思路，最後實現了可調脈寬灰度移位調制交流驅動晶元軟體的設計，在高達50mhz的時鐘下，模擬波形工作正常。
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