程序數字邏輯 的英文怎麼說

中文拼音 [chéngxùshǔzìluó]
程序數字邏輯 英文
programmed digital logic
  • 程 : 名詞1 （規章; 法式） rule; regulation 2 （進度; 程序） order; procedure 3 （路途; 一段路） journe...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 程序 : 1 （進行次序） order; procedure; course; sequence; schedule; ground rule; routing process 2 [自動...
  • 數字 : 1. （表示數目的文字; 表示數目的符號） figure; digit; numeral; character; numeric character 2. （數量） quantity; amount
  • 邏輯 : logic
  1. The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block

    設計的riscmcu採用14位字長指令總線和8位字長數據總線分離的harvard結構和二級指令流水設計，並使用硬布線邏輯代替微程序控制，加快了微控制器的速度，提高了指令執行效率。
  2. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  3. In fact, we use the digital way directly to synthesize sine wave

    摘要數字電路技術課程的知識難點是時序邏輯電路的設計。
  4. Complex programmable logic device ( cpld ), usually used to develop asic, is widely used in digital system to accomplish complex combinational and sequential logic

    復雜的可編程邏輯器件（ cpld ）廣泛地用於數字系統中，常用作設計自己的專用集成電路，可實現復雜的組合邏輯和時序邏輯。
  5. In the modulation / demodulation circuits, cpld is selected as platform of the digital logic part, which includes series - shunt / shunt - series transform, difference coding and sample verdict

    調制/解調電路中，串並/並串變換、差分編/解碼和抽樣判決等數字邏輯部分是以cpld作為開發平臺，論文給出了實現上述功能的vhdl程序及模擬、測試結果。
  6. And, the thesis mainly presents the research on the key technique of the dataflow control, including the realization of the pci interface control, the control of the sram memory that read or written by fpga, the pretreatment and the output control of the image and the intercommunication between pc and fpga. and then, it presents the design and the realization of the pc application program. in the end, it presents the debugging stepps and the application of the system.

    本文的重點在於介紹高解析度實時圖像處理系統的fpga控制邏輯設計，主要研究了該數字圖像處理系統中影響系統實時處理速度的數據流控制技術，如pci介面控制、 fpga與外部ram的高速讀寫控制、圖像的採集預處理，圖像的輸出控制等，本文還介紹了高解析度實時圖像處理卡的上位機應用程序設計與實現，本文的最後介紹了系統的調試及應用。
  7. Then we explicate the hardware design in details, including implementing ad convert, extending multiple serial communications and external memory, and using cpld do some logic controls. thereby we implement abundance simulation interface, flexible digital interface and serial communication interface. at last we describe the software design, including software design of cpld basing on vhdl and software design of dsp

    本文首先介紹飛行模擬訓練系統的主要組成；接著說明飛控計算機整體系統方案的設計；然後詳細說明飛控計算機硬體平臺的設計，包括ad轉換、多串口通信、外部存儲器的擴展以及採用可編程邏輯器件cpld實現電路的邏輯控制等幾部分，體現了系統豐富的模擬介面、方便靈活的數字介面和串列通信介面；最後是軟體部分的編程，包括cpld部分的硬體描述語言程序設計，和dsp部分相關的程序設計。
  8. Semiconductor devices - integrated circuits - digital integrated circuits - blank detail specification for programmable logic devices

    半導體器件.集成電路.數字集成電路.可編程序邏輯設備的空白詳細規范
  9. For insuring the robustness and high - efficiency of ett utility program, pipeline technology with logical condition of power builder and time - marker table created in data warehouse are adopted while designing and developing ett utility program

    為了確保ett實用程序的健壯性和高效性以及數據倉庫中數據的一致性和完整性，在ett實用程序的設計開發過程中採用了powerbuilder具有邏輯限制條件的數據管道技術，並在數據倉庫中設置了時間標記表和數字標記表。
  10. This course consists of lectures and labs on digital logic, flipflops, pals, counters, timing, synchronization, finite - state machines, and microprogrammed systems

    本課包括了數字邏輯、觸發器、 pal （可編程邏輯陣列） 、計數器、時序、同步、有限狀態機、和微控制系統方面的講課與實驗。
  11. The model, in this case, is the high - level language program - which, like all useful models, hides irrelevant detail about the idiosyncrasies of the underlying computing technology such as internal word size, the numbers of accumulators and index registers, the type of alu, and so on

    這種情況下，模式就是這個高級語言程序，它就像所有有用的模式那樣，隱藏了潛在的計算技術特性上的相關細節（比如內存字元大小，累加器的個數，索引寄存器， alu算術邏輯單元類型等等） 。
  12. The paper analyses its key circuit and software program structure. this full - digital controller is made up of dsp and implements single neuron adaptive pid computation, current pi computation, logical determination, pulse - fire and procession of protective signal etc. it also improves the reliability and availability of this control system

    本課題對控制器主要的電路結構及程序結構進行了分析，以dsp為核心組成的全數字式控制器完成了電流pi演算法計算，單神經元自適應pid演算法計算、邏輯判斷、脈沖觸發以及系統保護信號的處理等，提高了控制器的可靠性和可操作性。
  13. Both are used to separate the responsibility for rendering pages from the model and controller. both accept objects passed into them as an input argument, both allow inserting string values within code " expressions ", and allow direct use of java code to perform loops, declare variable, or perform logical flows " scriptlets ". both are good ways of representing the structure of a generated object web page, java class, or file while supporting customization of the details

    Jet與jsp非常類似：二者使用相同的語法，實際上在後臺都被編譯成java程序；二者都用來將呈現頁面與模型和控制器分離開來；二者都可以接受輸入的對象作為參數，都可以在代碼中插入字元串值（表達式） ，可以直接使用java代碼執行循環、聲明變量或執行邏輯流程式控制制（腳本） ；二者都可以很好地表示所生成對象的結構， （ web頁面、 java類或文件） ，而且可以支持用戶的詳細定製。
  14. The digital one includes spec, verilog coding, simulation, synthesis, floorplan, routeing, static timing analyze and drc / lvs check

    數字電路設計流程則包括：制定spec ， verilog代碼編寫，模擬，邏輯綜合，布局，布線，靜態時序綜合和drc lvs檢查。
  15. In this tutorial three artificial sets of elements will be used : lowercase, uppercase ve xnumber sets. for a human reader it is an easy task to recognize the set an element belongs to. but the computer does not have the apriori knowledge the human has and so the logic would have to be programmed into the handling program

    在本教程中，我們假定3個元素集合:小寫字母，大寫字母，以x開頭的數字ve xnumber ，盡管對於人類來說可以很容易的識別一個元素是屬于哪個集合，然而計算機並沒有人類這種演繹能力，因此這樣的邏輯必須要編寫到處理程序里去
  16. This image grab card uses saa7111 to translate the analogue signal to digital image data. after buffering in an fifo ram the data are read into computer by a universal pci interface chip, pci9052. finally the images are displayed on screen

    該視頻採集卡以fpga為邏輯控制中心，採用saa7111將四路視頻信號分別轉換為數字圖像數據，經fifo緩存后，由pci總線介面晶元pci9052將數據送入計算機，最後通過應用程序將圖像顯示出來。
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