統級 的英文怎麼說
中文拼音 [tǒngjí]
統級
英文
irrespective of size-
This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga
本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。Procedure for system - level temperature cycle endurance test
系統級溫度循環耐久性試驗程序Our technology competences are concentrated around mechatronics, system in package and digital systems
我們的技術強項主要表現在機電產品、系統級封裝和數字系統方面。Measurement challenges for on - wafer rf - soc test
晶圓上測試射頻系統級晶元的挑戰It is the base of manual changement of system - level model and auto - synthesis
此方法適合所有具有面向對象特性的系統級語言，可以作為系統級模型手工轉換或自動綜合的基礎。With the development of the network and the multi - processor system, the research, simulation and the impemeni of the system - level fault diagnosis which is the very important means to increase the reliability of the system, are becoming more and more important. on the system - leve1 fault diagnosis, based on the group theory of system - level fault diagnosis that has been put forward by pro f zhang, the paper constructs newly the theory bases, improves on the matrix method, reinforces and consummates group arithmetic of all kinds of test mode, for the first time, analyses and discusses the equation solution of all kinds of models, so al1 the consistent fault patterns ( cfp ) could be found, straightly and high efficiently, even if the sufficient and necessary condition of t - diagnosable is dissatisfied and the complexity of system - level fault diagnosis is greatly decreased, especialy in strong t - diagnosabl6 system. last the simulation system ' s function has been extended and the application hotspot and the development trend have been disscussed
本人在張大方教授等人提出的基於集團的系統級故障診斷的理論基礎上，重新構建了系統級故障診斷的理論基礎，定義了系統級故障診斷測試模型的三值表示；改進了系統級故障診斷的矩陣方法，重新定義了測試矩陣、鄰接矩陣、結點對、結點對的相連運算、極大準集團和斜加矩陣，由此能直觀、簡便地生成集團和極大獨立點集；補充和完善了各類測試模型的系統級故障診斷的集團演算法，通過定義集團測試邊和絕對故障集，簡化了集團診斷圖，由此能較易地找到所有的相容故障模式，即使不滿足t -可診斷性，大大減少了系統級故障診斷的復雜度，尤其是對強t -可診斷系統；首次分析探討了各類測試模型的方程解決，由此從另一角度能系統地、高效率地求出所有的相容故障模式（ cfp ） ：擴充了系統級故障診斷模擬系統的功能，快速、直觀和隨機地模擬實驗運行環境，進行清晰和正確的診斷，同時提供大量的實驗數據用於理論研究，優化演算法和設計。Hsupa ( high speed uplink packet access ) is the new technique of r6, first in this thesis, the hsupa physical layer is introduced in detail. then base on the physical layer technique characteristic, according to the 3gpp simulation requirements and system simulation requirements, the hsupa downlink and uplink can be constructed by using matlab. then the data channel and control channel can be simulated, so the channels performance can be realized, provide the results can be provided to the system simulation, these ground the future practical applications
Hsupa （ highspeeduplinkpacketaccess ） ? ?高速上行分組接入就是r6版本中的新技術，本文首先詳細介紹了hsupa物理層的技術特徵，然後以其技術特點為依據，按照3gpp的模擬需求和系統級的模擬需求，使用matlab構建hsupa的上下行物理層鏈路，對其數據通道和控制通道進行模擬驗證，從而了解通道的性能，為系統模擬提供模擬數據，為以後的實際應用打下基礎，達到預研的目的。The routing protocol in the scheme uses the basic concept of aodv for reference and makes necessary improvement to satisfy the delay and
通過系統級的模擬，得到使用本方案的eplrs通信網路性能，為eplrs系統的設計提供參考。In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future
第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpgaIn order to reduce the memory space of the system, ac3 program is optimized and hardware / software co - design method is used to optimize the memory space consumed in system level assemble level and hardware level
為減少系統的存貯耗費，針對ac3程序進行了存貯優化，並提出了一種應用軟硬體協同設計的方法，即從系統級、匯編級和硬體級進行存貯優化。Short for binder utility, an operating - system program that performs binding
聯編實用程序的簡稱，是一種能夠實現聯接和編輯的操作系統級的程序。System level electrostatic discharge simulator verification standard
系統級靜電放電模擬器驗證標準Function solution for system - level fault diagnosis based on chwa amp; hakimi fault model
故障模型的系統級故障診斷方程解決According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system
針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。System index trade - off methodology in concurrent design
并行設計中系統級指標權衡分析的方法研究Determining production - worthiness requires both unit - and system - level testing
決定其生產價值就需要從單元級和系統級全都進行測試。Based on the multidisciplinary design optimization, a multidisciplinary variable coupling design optimization method for non - hierarchic systems was presented, and its basic ideas and working principle were given, to handle the coupling between subsystems, a coupling function was established by the ideal point during system - level coordination, which was used to coordinate independent optimization of the subsystem and finally obtain the global optimal solution
摘要基於多學科設計優化原理，提出了面向非層級復雜系統的多學科變量耦合優化設計方法，闡述了其優化設計的基本思路和工作原理通過設置理想耦合點，構造了耦合函數，使子系統在各自獨立優化設計的同時，在系統級的協調下達到耦合關系的滿足，並使系統得到總體上的優化。With vast land, mountain view, presidential - class cypress villa, conference enters, swimming pool, herbal pool, and restaurant, it amazes all the guests
投資上億的檜木總統級別墅、獨棟木屋和綜合會議中心、泳池、藥浴池、餐廳…宛若國際級的渡假設施讓人驚嘆不已。An application exception represents the occurrence of a business logic error : withdrawing more than an account balance, reserving a seat which is already reserved, getting a credit card charge denied, etc. this is different from a system exception, which represents a system level error like running out of memory or running past the end of an array
應用程序異常表示發生了業務邏輯錯誤：取款超出了賬單余額、預訂已被訂出的座位、獲取已被凍結的信用卡的費用等等。這同系統異常不同，系統異常表示系統級別的錯誤，如耗盡內存或者數組越界。This paper presents a novel model and algorithm of rapid system level placement for cdp
本文提出了一種新的面向系統級并行設計規劃的快速布局模型與演算法。分享友人