線路緩沖器 的英文怎麼說

中文拼音 [xiànlùhuǎnchōngqì]
線路緩沖器 英文
line buffer
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 緩 : Ⅰ形容詞1 （遲; 慢） slow; unhurried 2 （緩和; 不緊張） not tense; relaxed Ⅱ動詞1 （延緩; 推遲） d...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 線路 : 1. [電學] circuit; line 2. [交通運輸] line; route
  1. In the proposed method, the controller takes the buffer length as congestion indication, takes sources quality and bandwidth utility as object function so as to learn on line. as the controller outputs, the coding rate for input traffic sources and the corresponding user percentage are used to adjust the cells " arrival rate to the multiplexer buffer. compared with the previous method where cells " arrival rate is tuned only by the encoding rate and the encoding rates for all input traffic sources are regulated in a body, the proposed method guarantee that the quality of cells are optimal while cell loss rate is minimized, which means quality of service is guaranteed

    在該方法中，擁塞控制器以緩沖區大小信元作為擁塞指示，以信源質量和帶寬利用率作為目標函數進行在線學習，控制器輸出包括信源編碼率及其對應的用戶數在全部用戶中所佔的百分比，即根據信源編碼率及對應的用戶百分數調整信源輸入流，從而克服了以往擁塞控制方法中僅僅調整編碼率帶來的對所有信源進行整體調整的缺陷，使控制系統在信元損失率最小情況下確保信源輸入流質量最高，從而有效地利用了網路帶寬。
  2. Main technic of giss webgiso thus function modules architecture and network topological structure are confirmed webgis system implements the basic function of electronical map, such as map zoonu pan, and the abundant query of geograph and database by using maplnfo mapxtreme for java as map server and jsp., java technico this system also can implement the routing of linesx analysing of buffer and so on0 this paper advances storage model of roads and pipelines topology data, efficiently solves the maintenace problem of network topology data of webgis and implements the shortest path algorathm based on webgis by improving it0 the system has better opening by suppling database interface of map ? the system has perfect on - line help and user forum and favorable interfaces and implementation of this system makes fundament for the further research of webgiso

    本系統利用mapinfomapxtremeforjava作為地圖服務器，採用jsp和java技術，實現了基於webgis的電子地圖的縮放、漫遊等基本功能，並具有豐富的圖文定位查詢功能；實現線路路由、緩沖區分析等輔助決策功能；構建了道路管線網路拓撲數據的存儲模型，有效地解決了基於webgis的網路拓撲數據的維護問題；對dijkstra演算法進行了一些改進，實現了基於webgis的最短路徑演算法；本系統提供了電子地圖數據庫介面，使本系統具有很好的開放性和通用性； webgis系統軟體具有完善的在線幫助和用戶交流論壇，人機界面友好。
  3. It eliminates the need for agent blocks to have specific knowledge of ram array behind it. it takes care of protocols and latencies in an effort to simplify memory access by the agent blocks. agent blocks " see " a single linear frame buffer, all paging and bank swapping is handled by the and is transparent to the agent blocks

    在嵌入式系統晶元中高速存儲器介面控制電路是系統必不可少的重要組成部分，由於有了存儲器介面的存在，使得系統內部客戶模塊不必專門了解存儲器本身的復雜特性，而只需關心傳輸協議和一些定義的遲滯參數，在客戶看來存儲器僅僅是一個線性的幀緩沖器，所有的換頁、區段切換都交由介面電路來處理，從而大大簡化了客戶對存儲器操作的復雜度。
  4. This card largely depends on three integrate chips to fulfill its function : 1 ) nic control main chip, corresponding the mac sublayer of ethernet, to realize csma / cd media access protocol, manage the sending and receiving buffers integrated on the chip and provide motherboard pci interface. 2 ) serdes ( serializing and deserializing ) chip, corresponding pcs and pma sublayers in ethernet, mainly to complete 8b / 10b coding and convert 10 bits parallel data to serial data, and convert them again at the receiving end. 3 ) fibre transceiver unit, completing light - electrical conversion of seri

    該網卡主要由3塊集成的晶元完成其功能，分別是i ）網路控制主晶元，對應于以太網的mac子層，主要完成csmaicd介質訪問協議，管理片上集成的發送和接收緩沖區，並提供和主板p0總線的介面： b ） s rd s （串列解串列化器）晶元，對應于以太同的pcs和pma子層，主要完成sb lob編碼並將10位并行的數據轉換為串列數據，在接收端完成相反的功能：涌）光纖收發器，完成串列數據的光電轉換功能。
  5. An algorithm of path - based timing optimization by buffer insertion is presented. the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation. and heuristic method of buffer insertion is presented to reduce delay. the algorithm is tested by industral circuit case. experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied

    提出了一種基於路徑的緩沖器插入時延優化演算法，演算法採用高階模型估計連線時延，用基於查表的非線性時延模型估計門延遲.在基於路徑的時延分析基礎上，提出了緩沖器插入的時延優化啟發式演算法.工業測試實例實驗表明，該演算法能夠有效地優化電路時延，滿足時延約束
  6. The pulse - peek sampling and adc module is able to catch a single and very narrow pulse in order to sample its peek value without being influenced by other pulses or noise. the pulse - peek sampling and adc module can also adapt itself to different rising edge of pulses, so it can scale different types of explorers made by our research institute

    X射線探測器定標分析系統的前端脈沖峰值採集及其轉換電路能夠實現單個快速脈沖的捕捉及對不同脈沖上升沿陡緩的適應，它對不同傳感器的放大信號特徵都有很好的適應性，對脈沖峰值采樣的結果具有很高的精度。
  7. The hardware designing include the interface with engine controller, such as d / a conversion. we chose the ad75089 which was produced by ad corp. this is a parallel port digital to analog conversion, and i give the presentation about its structure and connection scheme. in order to resolve the contradiction between faster computation and slower display, a buffer storage also needed

    第二部分詳細陳述了高速數據傳輸卡的軟、硬體設計過程，硬體設計包括dsp與pci總線的介面、 dsp與外部控制器的介面、以及電路卡上的擴展數據緩沖區的設計，並使用專門的工具軟體protel繪出全部硬體電路的設計原理圖。
  8. To closely investigate the uncertain nonlinear factors in the cushion process and simplify their influence for the sake of the mathematic modeling, an experimental rig is designed and constructed, for which the mechanical, hardwired and software tasks have been done. 5

    為了研究氣動緩沖和液壓緩沖器緩沖過程中不確定的非線性因素，在可接受的范圍內進行簡化以方便建立相關的數學模型，設計、搭建了氣動緩沖和液壓緩沖器建模用實驗臺，完成了機械、電路、軟體等多方面的任務； 5
  9. We give the effect result of different buffer in train longitudinal dynamics, and analyze the advantage and disadvantage of using different brake value and brake shoes

    本文還對裝備了不同緩沖器、列車制動系統，以及運行於不同線路和採用不同操縱方式的列車進行了縱向動力學的計算。
  10. Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired

    在超導rsfq數字電路模型的理論分析基礎上，論文中採用wrspice對超導rsfq數字電路進行時域模擬，得到了超導jtl傳輸線，緩沖器， rs觸發器， t觸發器，或門等基本邏輯單元電路以及電路參數。
  11. The internal processor bus described in sec. xx is connected to the external processor bus by a set of bus buffers located on the microprocessor integrated circuit

    Xx節所描述的內部總線通過一組位於微處理器集成電路內的總線緩沖器與外部總線連接。
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