編碼晶元 的英文怎麼說

中文拼音 [biānmǎjīngyuán]
編碼晶元 英文
mpeg
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 編碼 : encoded; code; coded; encrypt; codogram; coding編碼表 encode table; 編碼程序 builder; 編碼尺 code...
  1. In all kinds of complicated network, oriented linking and unlinking, communication frequency resource is strained, and bandwith to transmitting audio frequency signal is too restricted, complicated and fluky, while audio frequency data exponential have been increased in the last several years. under the circumstances, based on the research of predecessor, this paper studies wavelet analysis ' s maths gist and practices significance on signal process, and puts forward a optimized wavelet package condensation arithmetic to process audio frequency data, which gives attention to coding efficiency, multirate and compression delay. simulation experiment on the arithmetic has been done by matlab

    針對無連接和面向連接的各種復雜網路環境下，通信頻帶資源緊張，音頻傳輸帶寬有限且復雜多變，而各種音頻數據又日益增多的局面，本文研究小波分析在信號處理方面的數學依據和在數據壓縮方面的實際意義，在前人不斷工作的基礎上，提出了一種優化小波包變換編碼方案用於音頻數據的壓縮演算法，兼考慮了編碼效率、多碼率和壓縮時延多個方面，並在matlab環境下做了模擬實驗，對各種音頻信號及多種小波函數做了模擬結果比較，實驗結果證明該演算法可以在一定計算復雜度下可以很好地改進壓縮效果，達到多碼率下實現實時編解碼的過程，在高速dsp晶元等硬體設備支持下，可以有效應用於實際復雜多變信源編碼。
  2. With the developing of vlsi in recent years, high function dsp has been produced ( such as tms320 series dsp produced by ti ) and their cost is dropping. thus, this established the foundation for making complex speech coder practical and producible. the paper researched and discussed the fix - point real implementation of g. 728 by dsp tms320c5402 chip

    但是，近幾年來，隨著大規模集成電路（ vlsi ）的發展，已生產出高性能數字信號處理晶元（例如ti的tms320系列dsp晶元） ，而且其成本在不斷降低，這就為復雜的語音編碼器的實用化和產品化奠定了基礎。
  3. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  4. The encoder and decoders in the paper has been tested on the circuit board using the altera ’ s fpga of stratix gx ep1sgx25df672c7 with the system clock of 125mhz

    本文的編解碼器採用altera公司的fpga晶元stratixgxep1sgx25df672c7在系統時鐘125mhz的情況下完成了電路板測試。
  5. There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally

    首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。
  6. The system is consist of the main data processing board which is based onthe fpga device and fast ethernet phyceiver rtl8201l and a - law pcm data encoder and decorder chip msm7702 - 3, and the dial - up and display board which is based on mcu. the main board would carry out the core task of data processing, such as voice data packing and unpacking, the ethernet frame processing, protocol processing, call processing, etc. the dial - up and display board would carry out the task of display the ip address which is input by consumer and status of network during talk period from the main board, and so on. in the paper the system of lan ip telephone and the tcp / ip protocol is introduced firstly, then the fpga device is stated. after that the fpga - based hardware scheme is introduced in detail in chapter four

    系統以altera公司的acex1k系列的fpga和快速以太網控制器rtl8201l和語音編解碼晶元msm7702 - 3為核心構建了數據處理主板和以單片機為控制器的撥號顯示子板組成。數據處理主板的核心任務，包括語音數據處理、以太網幀處理、協議處理、呼叫處理等。撥號顯示子板則完成通話前的顯示用戶所撥過的ip地址，通話期間網路狀態的顯示等等。
  7. Introduces operation principle and interface circuit design of video input processor saa7111 and video output processor saa7185. 4

    介紹了可編程視頻輸入編碼晶元saa7111和可編程視頻解碼輸出晶元saa7185工作原理和介面電路設計。
  8. First an analog video signal is decoded by saa7 11 a to form a digital video signal complying with ccir6o1 which then is compressed by an special chip ibms42o, at last, the video es is packed with audio es to form ts by computer

    具體來說，是把模擬視頻源解碼成符合ccir601規范要求的數字視頻源，經專用的mpeg2編碼晶元壓縮形成視頻es流送入計算機，與一路音頻es流打包復用后形成一路ts流。
  9. It has application in dvd and htdv and dvb - c and video transmission in network, etc. two parts the principle of video reduced on mpeg - 2 standard and the designing of encoder and debugging on encoder are primarily expatiated on in this dissertation

    本文編碼器採用fujitsu公司的mpeg - 2編碼晶元mb86390用硬體來實現視頻信號的壓縮，編成mpeg - 2碼流，可應用於dvd 、數字電視、 dvb - c及視頻的網路傳輸等。
  10. This paper focuses on the research and implementation of these six key techniques. firstly, this paper researches the international standards for compression of digital video data, analyses how to compress analog video stream to mpeg - 4 with hardware. it is also involved in the techniques of net transmit of digital video data, such as net protocol, ip multicast, rtp / rtcp and so on

    本文主要是對智能視頻監控系統關鍵技術的研究與實現，主要體現在以下幾個方面: 1 、在視頻數據的壓縮方面，研究與分析了視頻壓縮的標準以及對mpeg - 4壓縮標準做了簡單的介紹，並分析了mpeg - 4的硬體實現方式，即使用硬體編碼晶元vw2010將視頻信號轉換為mpeg - 4格式的視頻流。
  11. Based on output wave of hs2260 encoding chip, this paper analyzes the encoding features of this chip and come up with the specific method of auto - adapted baud rate decoding of this chip by mcu and the method that was used in the long - click and double - click events recognition that was applied in remote controllor by this chip

    從hs2260編碼晶元的輸出波形入手，分析了該晶元的編碼特徵，提出了使用單片機對其進行自適應波特率解碼的方法，同時也提出了該晶元在遙控器應用中的長鍵及雙擊動作的識別方法。
  12. Introduces operation principle and interface circuit design of video codec adv611. 3

    介紹了新一代視頻編解碼晶元adv611的工作原理和介面電路設計。
  13. On designing of the encoder, by using the decoding for video chip saa7113 made in philips, analog video signal inputted realizes a / d conversion in analog / power block

    編碼器的設計中，模擬/電源塊主要實現的功能是對輸入的模擬視頻信號進行a / d轉換，解碼晶元採用philips公司saa7113 。
  14. This paper describes the error control coding of the flex paging system, with emphasis on the design and implement of the flex decoder circuit by means of the fpga technology

    本文介紹了flex高速無線尋呼系統中的差錯控制編碼技術，以及bch （ 32 ， 21 ）糾錯碼的構成和譯碼方法，重點討論了flex高速尋呼解碼晶元的fpga設計與實現。
  15. The application of hardware decoding circuit is widely, because it not only can be used on computer, but also can be used on consumer equipment like digital - tv and dvd - player. the avs and h. 264 standards and the architecture of digital video decoder chip are investigated in the thesis, and a high - definition multi - mode decoder soc chip is proposed. the chip can support avs level 4. 0 / 6. 0 and h. 264 main profile level 4. 0

    本文在研究了avs和h . 264視頻編碼標準和數字視頻解碼晶元系統結構的基礎上，設計了同時支持avs和h . 264的高清解碼soc晶元，能夠對avslevel4 . 0 / 6 . 0和h . 264mainprofilelevel4 . 0的高清晰度視頻碼流實時解碼。
  16. In this paper, we briefly introduced the performance of wave coding and vocoder, emphasizedly studied the principle and performance of variable rate vocoder q4401, including the internal construction and pins, qcelp coder & vocoder, pcm interface, cpu interface initialization process, command format and so on. we also designed a application circuit, with the experiment validated its performance. in this design, the pcm interface chip is tp3057, it was used to finish a / d transform, the compress coding was finished by q4401, the initialization and control were accomplished by 8051 singlechip

    重點是研究變速率語音編解碼晶元q4401的工作原理及性能。其中包括q4401的內部結構及管腳、 qcelp編碼方式、 pcm介面、 cpu介面、初始化過程、命令格式等，並在此基礎上，設計一個實際的應用電路，通過實驗，驗證其性能。在設計中用pcm介面晶元tp3057來完成從模擬信號到數字信號的轉換，再由q4401進行壓縮編碼，對q4401的初始化及控制由8051單片機來完成。
  17. The system adopts an advanced specific speech compression chip based on ambe algorithm. it can achieve high compression rate at 4 kb / s. the system first performs a / d conversion on analog speech input to obtain pcm signal and the pcm signal was encoded by the main compression chip

    它採用了比較先進的基於ambe演算法的專用語音壓縮編/解碼晶元，壓縮率高，可以將數字語音信號碼率壓縮至4kb / s ，且編碼速率可通過修改控製程序選擇。
  18. Now, the programmable chip ' s clock becomes faster and faster, the capability of programmable chip is improved very fast also, so more complex function can be implemented in one chip. this design can implement as jpeg coding chip in fpga, it can be used as ip core to other designs

    隨著可編程晶元時鐘頻率的不斷提高，晶元容量的不斷增大，可以在晶元上實現更復雜功能，這又使可編程晶元的應用更加廣泛。本設計可以單獨作為編碼器在fpga上實現，也可以作為一個ip核嵌入到其他設計中去。
  19. This dissertation discussed a solution of terminal in multimedia communication based on ethernet. and give a reference of constructing a platform of hardware, which consist of embeded cpu based on x86 core and chips of coding video. in linux os, we programmed to realize some functions, to control and change parameters of terminal on live

    本論文討論了一種基於以太網的多媒體通信終端機的設計方案，並給出了一個採用嵌入式x86 +內核的嵌入式處理器加專用視頻編解碼晶元組成的終端機實例，為多媒體通信終端機提供了一種硬體平臺的參考。
  20. Then a set of remote multimedia surveillance system project based on adv6oilc is provided, and the video matrix switcher and video image processing subsystem are presented expressly. finally, the software design is given

    然後提出了基於adv601lc編解碼晶元的遠程多媒體監控系統的方案，並對視頻矩陣切換電路和視頻圖像處理子系統進行詳細的闡述，並給出相關的軟體設計。
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