編碼電路 的英文怎麼說

中文拼音 [biānmǎdiànlù]
編碼電路 英文
coding circuit
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 編碼 : encoded; code; coded; encrypt; codogram; coding編碼表 encode table; 編碼程序 builder; 編碼尺 code...
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. With the developing of vlsi in recent years, high function dsp has been produced ( such as tms320 series dsp produced by ti ) and their cost is dropping. thus, this established the foundation for making complex speech coder practical and producible. the paper researched and discussed the fix - point real implementation of g. 728 by dsp tms320c5402 chip

    但是，近幾年來，隨著大規模集成電路（ vlsi ）的發展，已生產出高性能數字信號處理晶元（例如ti的tms320系列dsp晶元） ，而且其成本在不斷降低，這就為復雜的語音編碼器的實用化和產品化奠定了基礎。
  2. On one hand, the focal point that the interface circuit is designed lies in lining up the arrangement of the aerial data, have adopted one pair of ports ram to cooperate with the counter and realize the lining up of the data, on the other hand, interface focal point that circuit design transmission of data, part this finish mainly and interface of linkport of dsp, make data transmisst to dsp processor at a high speed, go on follow - up punish

    一方面，介面電路設計的重點在於對天線數據的整理排隊，採用了雙埠ram配合計數器實現數據的排隊，另一方面，介面電路設計的重點是數據的傳輸，這部分主要完成和dsp的linkport的介面，使數據高速傳給dsp處理器，進行后續處理。這個項目按照自上而下的設計流程，從系統劃分、編寫代碼、 rtl模擬、綜合、布局布線，到fpga實現。
  3. To extent the use of this 1c, some circuit blocks are added. in the design, digital circuits are used to process the signal and control the precision of coding. and some circuits are used in different time by several functions to reduce the number of transistors used and the dissipation

    電路設計中，為了便於信號處理以及控制編碼精度，採用數字的方法進行量階和預測碼的計算；同時，為了減小電路規模，採用了時分復用的概念，用同一部分數字電路實現量階調整和預測碼的生成，增加了編碼精度，減小了電路的規模和功耗。
  4. In that mainly including communication work mode, project argumentation of system, performance analyses and type choosing of communication transmitter - receiver and the design of antenna system, etc. in chapter 3, coding mode of msk and gmsk and the hardware circulation realization of modem are discussed in detail

    在第二章里，介紹無線電通信系統總體設計，按通信系統組成，逐項進行計算，主要包括通訊工作方式和體制的方案論證，通訊電臺性能分析、選型、參數，以及天線系統的論證等。在第三章里，詳細論述msk和gmsk編碼方式，以及用fx909實現數據機的硬體電路。
  5. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  6. William ， stallings, cryptography and network security, - principles and practics, second edition, prentice hall international, inc., 2000

    楊明等譯， 《密碼編碼學與網路安全：原理與實踐》 （第二版） ，電子工業出版社，北京， 2001 。
  7. The algorithm can not only eliminate the influence of the cumulative errors of the photoelectric code recorder, but also it can satisfy the requirement of the real - time control. a direct inverse model controller of fuzzy neural network with changeable structure based on takagi - sugeno inference is presented and it is used to the motion control of mobile robot. in order to avoid the obstacles successfully, detection results from ccd and ultrasonic sensors are fused by a fuzzy neural network, which acts as an avoidance controller

    包括移動機器人的融合自定位問題：移動機器人利用光電編碼器進行自定位，同時用擴展卡爾曼濾波器融合多個超聲波傳感器的測量值，採用回朔演算法將融合值用於復位光電編碼器，消除了光電編碼器累積誤差的影響，並能滿足實時控制的要求：並提出一種基於takagi - sugeno模型的變結構模糊神經網路直接逆模型控制器，並應用於移動機器人的運動控制；利用模糊神經網路避障控制器融合ccd攝象機與超聲波傳感器探測到的環境信息，以實現機器人的安全避障。
  8. The whole correlation - inheritance coding circuit system is designed, simulated and verified in verilog hdl on the candence systems

    採用了硬體描述語言verilog對整個相關繼承矢量量化圖像編碼電路系統在cadence系統上進行了西安理工大學碩士論文設計、模擬及時序驗證。
  9. Finally, considering the advantages and disadvantages of these algorithms, a trade - off algorithm is proposed. a corresponding vlsi coding circuit system is designed and verified with fpga

    最後結合各個演算法的優點，綜合考慮各方面性能，給出一個折衷的快速搜索演算法，並且設計出與演算法對應的編碼電路系統。
  10. The fpga post simulation results prove that the trade - off algorithm is an effective fast search algorithm of vq coding on the three aspects of reducing the coding time, improving the reconstructed image quality, and lowering the difficulty of vlsi implementation

    該編碼電路的fpga實現及fpga驗證結果表明，本文提出的快速演算法大大地減少了編碼時間、有效地提高了恢復圖像質量，同時也降低了硬體實現的難度。
  11. Then, this paper presents an improved t measuring speed method basing on t measuring speed method, and simultaneously realizes speed and angle measuring with two quadrature encoder pulse circuits of tms320lf2407a. the measuring speed formula is amended based on measuring speed error analysis

    其次，在t法測速的基礎上提出了一種改進的t法測速法，並利用tms320lf2407a的兩組正交編碼電路同時實現速度與角度測量，在分析測速誤差的基礎上，對測速公式進行修正。
  12. This thesis focuses on the ingress process module of ctu, which translates c - 5 dcp format to rainier 4gs3. the specification analysis, architecture and logic design, functional simulation testbench design, synthesis report and testing result are discussed in this thesis. the research work mainly includes : the specification analysis and design requirements of ctu logic ; the architecture and logical design of ingress process module, which includes receive control fsm, send control fsm and cell position adjustment logic ; the performance improvement of ingress process module to receive and transmit data cell at the full line speed

    本論文的主要研究工作包括：通信協議轉換邏輯的功能分析和設計需求；通信協議轉換邏輯上行方向的系統分析及體系結構設計，包括上行接收狀態機、發送狀態機、信元內位元組位置調整機制等的設計；通信協議轉換邏輯上行方向的線速設計，主要是上行接收的線速設計，要使用流水設計技術；提出了高速實現roundrobin調度策略的實現方法，並設計實現了桶式移位器和優先級編碼電路；應用bfm模擬模型設計了上行處理各模塊的模擬testbench ，完成了各級模塊的模塊模擬和系統集成模擬。
  13. Secondly, the encoder circuit of quasi - cyclic which can realize low encoding complexity are designed and implemented. three encoder circuit are designed respectively with feed shift - registers and logic gates : sraa - based serial qc - ldpc encoder ; sraa - based parallel qc - ldpc encoder ; two - stage qc - ldpc encoder

    採用反饋移位寄存器與邏輯門設計了三個典型的編碼器電路:基於sraa電路的串列準循環ldpc碼編碼器;基於sraa電路的并行準循環ldpc碼編碼器;二階編碼電路。
  14. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。
  15. There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally

    首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。
  16. Based on the realization of the encoder / decoders, this scheme aims at the highest rate downstream frame, and has realized the parallel fec circuit and scrambler complying with the protocols and maken a simulation. the fprme decoder is advanced in the world. the parallel fec circuit completely conforms to the itu - t protocols, and has important practical value

    在rs （ 255 ， 239 ）硬體編碼器/解碼器實現的基礎上，本文按照gpon協議要求，針對gpon中最高速率2 . 488gbps的下行幀，通過設計復雜的操作時序，實現了符合協議規定的32位并行fec編解碼和解擾碼電路，並作了模擬。
  17. The circuit of assembling frame and splitting frame based on ram and fifo are designed ( realized frame synchronization ). the two 3b4b converting circuits are designed ( realized one circuit ). the nrz, rz, manchester code converting circuits are designed

    4 、設計了基於fifo和ram的兩種組幀和拆幀電路（實現了幀同步碼檢出） ；設計了兩種3b4b編譯碼電路（實現了一種） ，針對nrzi 、 rz和曼碼各設計了一個編譯碼電路。
  18. The results of p & r demonstrate that this design constructs a rs encoding / decoding circuit with a 3. 2k internal fifo cache embedded, at the scale of 46k gates. its encoding and decoding speed are 66mhz and 47mhz respectively

    布局布線后結果表明本文所設計的rs編碼器的速度可達到66mhz ；解碼速度可達到47mhz ，電路規模為4 . 6萬門，包含有3 . 2k的內部緩存fifo的rs編/解碼電路。
  19. An application of logic devices able to program to the decoding circuit

    可編程邏輯器件在譯碼電路中的應用
  20. On the basis of analyzing the old system and theory, the element circuits of wireless digital audio transceiver modules are designed in detail including the digital audio encoding and decoding circuits with the surrounding circuits, the fsk circuit based on pll frequency synthesizer, the power amplifier circuit, the frequency discrimination and agc circuit

    在分析原系統結構和理論的基礎上，完成了整個無線數字音頻傳輸模塊各單元電路的設計。主要包括有數字音頻編碼和解碼電路及外圍電路的設計、基於鎖相頻率合成器理論的fsk電路設計、功率放大器的設計、鑒頻與agc控制電路的設計。
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