緩沖器單元 的英文怎麼說

中文拼音 [huǎnchōngqìdānyuán]
緩沖器單元 英文
buffer unit
  • 緩 : Ⅰ形容詞1 （遲; 慢） slow; unhurried 2 （緩和; 不緊張） not tense; relaxed Ⅱ動詞1 （延緩; 推遲） d...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. First, it is compressible and cushiony ; second, it can be transported to a long distance with a little power loss ; the last, its flux and velocity of flow are quite high, so the reaction time of the operators can been considerably shortened. aiming to solve the problems of vibrating machinery such as short life - span, poor cushion and high energy consumption, the writer, on the basis of characteristic of pneumatic mentioned, contrives a set of valve controlled pneumatic vibrator, which has larger output vibrating force and longer life - span with simple structure. then, it is applied to drive a vibrating screen and the result is fairly well

    文中針對氣動技術本身的特性及優點，如：可壓縮，具有緩沖性；能耗損失小，便於遠距離輸送；流量大、流速高，執行元件響應速度快等，以解決振動機械在應用過程中的緩沖、能耗以及使用壽命等問題為目的，設計出一套輸出激振力大、結構簡單、使用可靠的閥控氣動激振器，並將其成功地運用到振動篩上，取得了較好的效果。
  2. The design of each functional module, including the bridge selected module, mlb slave state machine, buffer, ahb master state machine, arbiter. 4

    各功能模塊的設計，包括橋選擇單元、 mlb從狀態機、緩沖區、 ahb主狀態機，仲裁器； 4
  3. By default mmus are implemented and they are constructed of 64 - entry hash based 1 - way direct - mpped data tlb and 64 - entry hash based 1 - way direct - mapped instruction tlb

    默認的存儲器管理單元實現由基於64個散列入口的單通道直接映射的數據后備式轉換緩沖區和基於64個散列入口的單通道直接映射的指令后備式轉換緩沖區組成。
  4. A processor architecture is disclosed including a fetcher, packet unit and branch target buffer

    母案摘要:揭露一種包含指令取器、封裝單元及分支目標緩沖器的處理器架構。
  5. Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired

    在超導rsfq數字電路模型的理論分析基礎上，論文中採用wrspice對超導rsfq數字電路進行時域模擬，得到了超導jtl傳輸線，緩沖器， rs觸發器， t觸發器，或門等基本邏輯單元電路以及電路參數。
  6. With regard to the buffer storage of the module, a new method called two - lever buffer structure is adopted, in which the fpga ‘ s internal ram cells is the first level buffer and the sdram of embedded system is the second level buffer

    2 .在設備的緩存方案上採用二級緩沖結構，利用fpga內部提供的存儲器單元作為第一級緩沖，利用嵌入式系統中的sdram作為第二級緩沖，實現了多通道、大規模緩存技術。
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