行同步信號 的英文怎麼說

中文拼音 [hángtóngbùxìnháo]
行同步信號 英文
horizontal synchronizing signal
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  1. The synchronous signal of mc1311 cmos camera is shaped by monostable trigger 74ls221

    使用單穩態觸發器74ls221對送給mc1311cmos攝像機的同步信號進行整形。
  2. The second, the main work in the paper is discussed. they are include : the theory and character of electromagnetic leaking from a computer ; the theory of accumulation mean filter and pectination filter ; the analysis of synchronous signal precision, at 10 - 12 second level, for stably intercepting ; the technology requirement of receiver and data acquisition board for clearly displaying the images recovered from the intercepted data

    本文從計算機視頻電磁泄漏和數字濾波器兩方面的基本理論出發，詳細論述了計算機視頻信息電磁泄漏的原理及特點，指出視頻泄漏信息的頻譜是以行頻為周期的譜線；分析了重加濾波器和梳狀濾波器的性能；分析了視頻泄漏信息截獲的條件；推導出穩定截獲視頻泄漏信息需要對同步信號的精度控制在皮秒級；論述了清晰再現對接收機和數據採集卡的技術要求。
  3. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  4. It can separate sync signals from ntsc, pal and secam video signals, and produces composite sync output signal, back porch output signal, horizontal sync signal, vertical sync signal and odd / even field output signal

    它可以對ntsc 、 pal 、 secam制式的視頻信號進行同步分離，獲得所需的同步信號，還能準確地輸出復合同步、后沿輸出、行同步、場同步和奇/偶場輸出信號。
  5. The function of video frequency gathering board is to reveal the compound television signal from the computer to carry on a / d transforms, rgb separation processing and so on, output 24bits rgb signals and the synchronized signals. these functions were finished by video frequency decoding chip saa7111 made by philip corporation

    視頻採集板的功能是利用philip公司的視頻解碼晶元saa7111 ，對計算機顯卡輸出的復合電視信號進行a / d轉換， rgb分離等處理，輸出24位rgb信號和同步信號。
  6. Moreover, the higher harmonic order is, the lower distinguishability, and, as a result, the assessment accuracy becomes bad. considered its prominent localization both in time - domain and in frequency - domain, wavelet is used to the field of assessing harmonic impedance for the first time. we choose chaari wavelet because of its special band frequency characteristic, which can stratify signals synchronously and locate the distortion time precisely in assessing harmonic impedance

    選取chaari小波為母小波，利用其特殊的帶通特性，對在公共連接點（ pcc ）采樣得到的電壓，電流畸變波形進行同步分層， 「突出」信號的畸變部分，提高了被分析信號的「信噪比」 ，以利於諧波阻抗估計準確度的提高。
  7. Based on the analysis of the driving theory of tft - lcd and the characteristic of lvds interface, we designed a drive circuit to control the horizontal / vertical synchronization signals and pixel signal, this drive circuit has a lvds interface. we make and debug the drive circuit by using performance - to - price fpga ep1c3t144 and lvds transmitting chip ds90c387

    在深入分析了液晶顯示器驅動原理和lvds介面特性的基礎上，基於fpga設計了控制顯示器行/場同步信號和顯示像素信號輸出lvds介面的驅動電路，並採用高性價比的fpga晶元ep1c3t144和lvds發送器晶元ds90c387製作和調試了相應的電路。
  8. The technology of compression of the rf synchronous information is comparatively low and secure and it can also produce high quality descrambling signals

    射頻行同步信號抑制的加解擾技術成本較低，技術比較成熟，電路實現也較為簡單。
  9. This project uses the single chip machine mcs - 51 as its fundamental controlling unit and adopts many digital chips. scrambling is fulfilled by compressing some of the synchronous tips carried by rf signal

    本方案以單片機mcs - 51作為加解擾系統的核心控制器件，通過將有線電視射頻信號的某些行同步頭壓縮掉的方式實現對電視信號的加擾。
  10. Synchronized drive module produces horizontal drive signal in synchronization with horizontal synchronization signal and field drive sawtooth in synchronization with vertical synchronization signal. these signal drive scaning sytem of slltv

    同步驅動模塊產生與行、場同步的行同步驅動信號和場鋸齒波驅動信號，用於驅動激光電視的掃描系統。
  11. This dissertation adopts a universal digital ds / dmpsk modulation and demodulation scheme which is based on fpga. this scheme adopts quadrature balanceable modulation, intermediate frequency sampling, digital matched filtering, delay differential demodulation techniques and so on. it directly processes the digital signals on intermediate frequency without down - conversion, and doesn ’ t need pseudo random codes synchronization and carrier wave extraction circuits

    本文採用了一種基於fpga的通用數字調制解調方案，該方案在調制端採用了正交平衡調制技術，在解調端採用了中頻帶通采樣、數字匹配濾波、延時差分解調等技術，直接在中頻上進行數字信號處理，不需要進行下變頻，也不需要增加額外的偽隨機碼同步捕獲和載波提取電路。
  12. The system is able to complete the data sample of 32 signals input, and has the ability to sample simultaneously of per 4 signal inputs. the conversion is 8 bits, and the sample rate of per channel is not less than 400hz. in addition, this data conversion system also have the ability of data storage without power supply, and the data size in flash memory is amount to sample 5s " of 32 signal inputs

    整個採集系統完成對32路輸入信號的采樣，而且可對每4信號路進行同步采樣， ad轉換精度為8位，每路信號采樣率不低於400hz ，另外系統還具備斷電數據保存功能，採用flash存儲器保存5秒的采樣數據，同時也具備與計算饑的epp并行通信介面。
  13. The constitution, interface and control principle of main circuit, rectifier control module, inverter control module, generator ' s rotor speed and rotor position measuring module, information exchange module are discussed. specially, the methods of implementing signals level match in multi - voltage system, synchronizing with pc in parameters measurement and measuring rotor speed and rotor position with high precision are explained in detail

    文中討論了主電路、整流器控制模塊、逆變器控制模塊、電機轉速和轉子位置測量模塊以及信息交換模塊的組成、介面方法和控制原理，詳細說明了系統中實現不同電壓等級間信號電平匹配的方法、系統與上位機進行同步參數測量的方法以及實現高精度電機轉速和轉子位置測量的方法。
  14. In transmission system, the original signal is modulated to ofdm signal after be coded in dpsk. and in receiving system, the modulated ofdm signal is synchronized and demodulated

    在發射端，將以一定速率輸入的二進制信息在進行dpsk編碼后調制到基帶ofdm信號上，在接收端，對已調制的ofdm信號進行同步和解調。
  15. It produces the i and q signals, limits their pass bands, uses them to modulate the subcarrier in a quadrature and adds the moduled subcarrier to the luminance y, blanking and synchronizing signal waveform

    它首先分離出i信號和q信號，指定了它們的傳輸頻帶，並用它們對副載波進行正交調制，然後將調制過的副載波信號疊加到亮度信號y和同步信號波形上。
  16. At the same time, using two - terminal voltages and currents sampled by the medium - speed sampling and processing unit synchronized by the pulse per second ( 1pps ) of gps, the fault locator can realize accurate double - ended steady - state location

    同時，線路兩端的測距裝置利用gps的同步秒脈沖信號（ 1pps ）控制各自的中速采樣處理單元對線路的電壓、電流信號進行同步采樣，用這些同步採集到的數據還可以實現精確的雙端穩態法測距。
  17. The blind synchronization method based on cyclostationarity is firstly analyzed in the downlink. simulations of the method are carried out under different channel conditions. the performances of the method are analyzed, and then compared with the blind method based on the cyclic prefix of ofdm symbols, thus the validity of the method is proved

    本文首先在下行鏈路中分析了基於ofdm信號的循環平穩特性的盲同步信息估計演算法，並在多種通道條件下進行了計算機模擬，對基於ofdm信號循環平穩特性的估計器的性能進行了分析，並與基於ofdm信號循環前綴的ml演算法的估計性能進行了比較，從而證明了提出演算法的有效性。
  18. In this method, each routing node runs a same ospf dameon and they do the routing computation and protocol processing independently based on their own warr. ospf damenoas commuciate by message delivery, with little semaphores needed to do the synchronization work between the dameons, and so we can get highly parallel degree between the dameons

    該方案中，各個節點運行相同的ospf進程，並基於各自warr獨立進行路由計算和協議處理，進程間通過消息傳遞的方式進行通信，不需要太多的信號量進行同步，因此有很高的并行度。
  19. The system employs multicarrier modulation ( mcm ) technique as the modulation method, and linear frequency modulation ( lfm ) signal as the synchronization signal and digital signal processor ( dsp ) as the hardware ' s core chip

    該系統選用多載波調制技術進行調制，選用線性調頻信號為其同步信號，選擇數字信號處理器為硬體核心晶元。
  20. Take the hoc based blind modulation detection algorithm as an example, the relationship between the blind modulation detection algorithm and synchronization is investigated. an unproved detection algorithm robust to frequency offset is proposed which solves the problem caused by the error in carrier synchronization. how to synchronize a received signal with unknown modulation type is studied and a blind algorithm to estimate symbol timing of the signals with unknown modulation type is presented

    研究了載波同步和碼元定時同步與調制方式盲檢測演算法的關系；以自適應單載波中高階累積量調制方式盲檢測演算法為例，對于載波同步誤差引起的頻偏問題，提出一種基於頻偏穩健的mdpsk信號調制方式盲檢測演算法；對于未知調制方式信號的定時同步問題，提出一種盲定時估計演算法，該演算法可以估計mdpsk和mqam信號的定時同步信息，實現數字信號的同步分類；提出了一種基於調制方式盲檢測的自適應接收機結構，把調制方式盲檢測，信噪比估計和同步解調聯合起來進行，實現調制方式隨通道質量而自適應變化的信號的正確接收。
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