行譯碼器 的英文怎麼說

中文拼音 [hángyìmǎqì]
行譯碼器 英文
line decoder
  • 行 : 行Ⅰ名詞1 （行列） line; row 2 （排行） seniority among brothers and sisters:你行幾? 我行三。where...
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. The control unit decodes the eighteen bits, so that the computer knows what we want it to do next.

    控制器對這18位字進行譯碼，於是計算機就知道我們要它下一步做什麼。
  2. The interpretation is carried out by the instruction decoder.

    該翻譯借指令譯碼器來進行。
  3. Turbo codes represent the new code structures, which consist of pccc ( parallel serially convolutional code ) and sccc ( serially concatenated convolutional code ). in this paper, the background of turbo codes are firstly introduced, which includes the base principle of error correction code 、 block code and convolutional code ; the principle of turbo code and the iterative decoding is secondly expanded ; the key decoding algorithm : a revised map algorithm and iterative decoding theory are detailed ; then, a new turbo code structure : hccc ( hybrid concatenated convolutional code ) is presented, and the capacity of this code method is analyzed, the average capacity upper bound is derived ; at last, this code is simulated on awgn ( additive white gaussian noise ) channel and rayleigh fading channel

    本文首先介紹了turbo碼的背景知識，包括差錯控制的基本原理、分組碼和卷積碼；然後闡述了turbo碼的基本原理，包括turbo編譯碼器結構及迭代譯碼原理；較為詳細地描述了關鍵的譯碼演算法： ?種改進的最大后驗概率（ map ）譯碼演算法及迭代譯碼演算法；提出了一種新的turbo碼結構：混合turbo碼（混合級聯卷積碼） ；並用編碼性能聯合界分析方法對混合turbo碼進行了性能分析，得出了其平均性能上界；並在高斯白噪聲通道和瑞利衰落通道上分別作了一些應用研究及計算機模擬實驗。
  4. We mainly improve the calculation of the fano metric on the basis of the original decoding algorithm, which enhance the decoder ’ s speed

    並在原有演算法的基礎上進行了一些改進，主要是針對其fano度量計算的改進，提高了譯碼器的工作速度。
  5. Making logical designs with the integrated decoder

    用集成譯碼器進行邏輯設計
  6. The decoder is compiled and simulated in ep1c12q240c by quartusii - 5. 0. the different error style is added to the sequence received in emulated channel. correspondingly, the correct decoding results are attained at the output terminal

    在quartusii - 5 . 0模擬環境下以cyclone系列的ep1c12q240c為目標晶元對譯碼器進行了編譯和模擬，在接收序列中加入不同的錯誤類型，相應的在譯碼器輸出端得出了譯碼后的正確譯碼結果，驗證了設計方案的正確性。
  7. A program that decodes instructions written as pseudocodes and produces a machine language program to be executed at a latter time

    一種實現以下功能的程序:對寫成偽碼形式的指令進行譯碼，產生一種機器語言程序以供需要時執行。
  8. The at 2 scale based on the internal area - time lower bound of the viterbi decoder is analyzed. and the at 2 scales of three vlsi realization algorithms ( m - step decoder algorithm, flow and block decoder algorithm, and sliding block decoder algorithm ) are deduced. in succession, a fully new algorithm named ring - vd algorithm designed by ourselves is put forward, and its at 2 scale is also fetched

    分析並推導了viterbi譯碼器基於內部信息流的vlsi面-時下界at2尺度;推導了已有的三種viterbi譯碼器的vlsi高速實現演算法（ m步譯碼演算法、流水式塊譯碼演算法和滑動塊譯碼演算法）的at2尺度;提出了一種新的環形vd演算法，並推導了它的at2尺度;對四種viterbi譯碼器的vlsi高速實現演算法進行了比較分析。
  9. Serial algorithm improves decoding performance greatly ; serial algorithm finds the better trade - off between performance and complexity, it is a good decoding algorithm with high application value. ( 5 ) introduce the background of quantized decoding and basic theory. analyse effect of quantized decoding, research the impact of limited quantized to serial decoding, and present feasible project for quantized decoding

    （ 5 ）介紹了量化譯碼的背景和量化原理，分析了量化譯碼對譯碼器實現的重要作用，基於串列譯碼演算法，以消息種類的不同分別研究了有限長量化對譯碼性能的影響，並提出可行的串列量化譯碼方案，其性能接近連續譯碼性能。
  10. Therefore, the research targets of this dissertation are to realize the coding and the decoding of stbc after studying its theory

    本文在研究了空時分組碼的理論基礎上，對其編譯碼器進行了硬體模擬實現。
  11. The research for key techniques of turbo codes is processed. it includes, ? the design of optimal component codes and the performance of asymmetric turbo codes are analyzed ; ? a search algorithm for short random interleaver based on the distance spectrum and ids criteria is carried out and simplified ; ? random puncturing method to improve the weight distribution of turbo codes with some special code rates is analyzed and simulated. ? the effect of different schemes of trellis termination to the performance of turbo codes is analyzed ; ? a new low complexity decoder structure is provided ; 5

    對turbo碼的部分關鍵問題進行分析和改進，主要包括： ?分析了最優分量碼的設計和非對稱turbo碼的性能； ?設計了基於距離譜和ids的短隨機交織器搜索演算法並進行了簡化； ?提出了採用隨機刪余方式改善特定高碼率turbo碼重量分佈特性的方法； ?分析了不同編碼器狀態歸零方案對turbo碼性能的影響； ?提出了一種降低實現復雜性的turbo迭代譯碼器結構。
  12. Retransmitted sequences of the inner code and packets are combined with previously transmitted packets to be progressively decoded by the same viterbi decoder. the extrinsic information will be exchanged between outer and inner codes

    接收端，重傳的數據包以及內碼校驗序列與前面已經校驗無錯的數據包組合起來，由同一個維特比譯碼器進行累進譯碼。
  13. Since this decoder has high error - correcting speed and regular structure, it may apply to data transmission and storage to decrease error rate

    由於該譯碼器有較高的糾錯速率和規則的設計結構，使它可以方便地用於數據傳輸和存儲過程中進行差錯控制。
  14. The vd is composed of four functional units : 1 ) the branch metrics unit ( bmu ) ; 2 ) the add - compare - select unit ( acs ) ; 3 ) the path metrics unit ( pmu ) ; 4 ) the survivor memory unit ( smu ) ; regarding the power dissipation of the viterbi decoder, the smu is the hottest spot in the viterbi decoder due to the frequent memory accesses. there are two traditional techniques for the realization of survivor memory unit in viterbi decoder - - register exchange ( re ) and trace back ( tb ) method

    這是當前開展低功耗邏輯優化的重要方面，也是本課題採用的方法。 viterbi譯碼器主要由四個功能單元組成:分支度量單元（ bmu ） ，加比選單元（ acs ） ，路徑度量存儲單元（ pmu ） ，倖存路徑存儲和輸出單元（ smu ） 。本文所做的viterbi譯碼器設計採用模塊化的設計方法，先對各個功能單元進行優化設計，然後將各個功能單元組合在一起，形成最終的譯碼器。
  15. The fifth chapter analyzes the fixed - point error of bp - based and normalized bp - based decoding algorithm, and gives the final simulation results of each decoding algorithm. with the simulation results and the considering the tradeoff between hardware complexity and error performance, some key parameters and finite precision analysis for the hardware implementation of ldpc decoder have been performed

    第五章對bp - based和normalizedbp - based演算法進行了定點模擬，對ldpc譯碼器的關鍵參數、硬體實現中的定點量化與字長精度問題進行了深入的研究，給出了對譯碼器硬體實現具有參考意義的研究結果。
  16. Re has a very complicated interconnections and needs a high power consumption. tb needs a large quantity of buffers and has long decoding delay. in this paper a modified register - exchange ( re ) method is presented, which reduce its memory access rate and its amount of memory, thus, reduces the power consumption

    在smu中，由於要進行頻繁的存儲器讀寫，功耗很大，成為整個viterbi譯碼器中消耗功率最大的單元，因此對smu單元進行低功耗設計對降低viterbi譯碼器的功耗起著非常重要的作用。
  17. Abstract : at first, this paper analyces the open defect of cmos ram address decoder, it comes out that one type open defect cannot be detected by march test algorithm, and then we give the test method of this type undetectable fault and the design scheme with built - in tolerance against hard - to - detect open defects

    文摘:對cmos存儲器中地址譯碼器的開路故障進行了分析和分類，得出了其中有一類開路故障不能用常用的測試演算法可靠的測試出，給出了測試該類開路故障的測試方法以及針對該類開路故障的容錯性設計方案。
  18. Three decoder architectures, parallel, serial and partially - parallel approaches, are analyzed in this thesis. a kind of novel partially - parallel architecture for decoding ldpc code is proposed. the trade - off between the performance of the decoder, hardware complexity and data throughout can be achieved with this partially - parallel architecture for the random parity check matrix

    論文分析了三種不同的譯碼器結構:并行結構、串列結構以及部分并行結構，並提出了一種新穎的部分并行結構的ldpc譯碼器，較好地解決了當校驗矩陣為隨機結構時，譯碼性能、硬體資源和數據吞吐量平衡的問題。
  19. Furthermore, this chapter analyzes the method and critical technique of the hardware / software co - design in general system and some concrete applications in this chip

    最後以rs譯碼器的實現為例來具體說明基於asip的軟硬體協同設計的主要過程，也對asip的構造和應用進行了分析。
  20. According to the structure of quasi - cyclic ldpc code, we can make a trade - off between hardware complexity and decoding throughput by applying semi - parallel architecture

    摘要利用準循環ldpc碼的結構特點，使用半并行結構的譯碼器可以實現復雜度和譯碼速率的有效折中。
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