襯底柵 的英文怎麼說
中文拼音 [chèndezhà]
襯底柵
英文
substrate gate-
This voltage creates a field across the gate oxide, which causes the adjacent p substrate to invert to n-type.
這一電壓在柵極氧化物層上產生一個電場，它導致毗鄰的P型襯底轉變成N型。In the dissertation, the effects of the air slide - film damping on the capacitive accelerometers having different slot structures which are completely or partly etched, and fabricated by the anodic bonding between silicon and glass and bulk silicon micromachining process are researched by changing the distance between the moving structure and substrate, the thickness of the structure, the width of the completely etched slot structure, the depth of the partly etched slot structure according to the two well known air slide - film damping models
對于橫向運動的體微機械器件，其周圍空氣表現為滑膜阻尼。本文基於滑膜阻尼的兩個模型，通過改變振子與襯底的間距、振子的厚度、刻透的柵槽的寬度、沒有刻透的柵槽的深度等參數，研究了這些參數對硅?玻璃鍵合工藝製作的體硅微機械電容式傳感器阻尼特性的影響。The low insertion loss is achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by dc biasing the transmit and receive nodes, which decreases the capacitances while increasing the p1db
通過優化mosfet的柵寬及偏置電壓可以降低插入損耗。在版圖設計中通過增加襯底接觸降低襯底電阻，從而減小插入損耗。另外，為接收和發送端提供直流偏置可以降低p1db 。We researched fabrication at different asputtering and annealing atmosphere, the different process conduced different electrical properties. we can conclude a higher annealing temperature and higher proportion of o2 during reactive sputtering favors the improvement of electrical performances of hfo2 dielectrics ; 4. the analysis of i - v curves of these devices displays different leakage current mechanism under different area of applied bias - voltage ; as to silc. there are different leakage current mechanism at influence of sil. c ; 5
研究表明，在優化工藝條件下制備的hfo _ 2介質層中，襯底注入條件下由於其較低的體和界面缺陷密度，漏電流的輸運機制主要以schottky發射為主; silc效應導致hfoz / si界面缺陷態的增加，從而使得襯底注入條件下，柵泄漏電流機制不僅有schottky發射還有f一p發射機制起主要作用; 5 ）初步研究了氮化的hfo : （ hroxny ）柵介質的電學特徵。The author ' s main contributions are outlined as following : first, the roles of hot electron and hole in dielectric breakdown of ultra - thin gate oxides have been quantitatively investigated by separately controlling the amounts of hot electron and hot hole injection using substrate hot hole ( shh ) injection method. the changes of threshold voltage have been discussed under different stress conditions
主要研究結果如下：首先，利用襯底熱空穴（ shh ）注入技術分別控制注入到超薄柵氧化層中的熱電子和空穴的數量，定量研究了熱電子和空穴注入對超薄柵氧化層擊穿的影響，討論了不同應力條件下的閾值電壓變化。This voltage creates a field across the gate oxide, which causes the adjacent p substrate to invert to n - type
這一電壓在柵極氧化物層上產生一個電場，它導致毗鄰的p型襯底轉變成n型。分享友人