解碼晶元 的英文怎麼說

中文拼音 [jiěmǎjīngyuán]
解碼晶元 英文
alc101a
  • 解 : 解動詞（解送） send under guard
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 解碼 : decoding; decipher; decode
  1. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  2. The paper is to design analogue lowpass filtering circuits with high performances. the circuits are used directly as anti - alias filters in an analogue front - end of video decoder ic ( integrated circuit )

    =本文旨在設計高性能的模擬低通濾波電路，用作視頻解碼晶元模擬前端中的抗混疊濾波器。
  3. In this dissertation the ts demultiplex task and ac - 3 decoding task in mpeg - 2 protocol are scheduled by 2 policies. one is the buffer - drive policy and the other is deadline - drive policy. some experiments have been done to confirm the policy and the arguments of the scheduling

    本文根據hdtv信源集成解碼晶元的工作原理，對mpeg - 2協議中的ts流解復用任務和ac - 3音頻解碼任務提出緩存驅動和時限驅動兩種調度策略。
  4. The function of video frequency gathering board is to reveal the compound television signal from the computer to carry on a / d transforms, rgb separation processing and so on, output 24bits rgb signals and the synchronized signals. these functions were finished by video frequency decoding chip saa7111 made by philip corporation

    視頻採集板的功能是利用philip公司的視頻解碼晶元saa7111 ，對計算機顯卡輸出的復合電視信號進行a / d轉換， rgb分離等處理，輸出24位rgb信號和同步信號。
  5. There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally

    首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。
  6. The system is consist of the main data processing board which is based onthe fpga device and fast ethernet phyceiver rtl8201l and a - law pcm data encoder and decorder chip msm7702 - 3, and the dial - up and display board which is based on mcu. the main board would carry out the core task of data processing, such as voice data packing and unpacking, the ethernet frame processing, protocol processing, call processing, etc. the dial - up and display board would carry out the task of display the ip address which is input by consumer and status of network during talk period from the main board, and so on. in the paper the system of lan ip telephone and the tcp / ip protocol is introduced firstly, then the fpga device is stated. after that the fpga - based hardware scheme is introduced in detail in chapter four

    系統以altera公司的acex1k系列的fpga和快速以太網控制器rtl8201l和語音編解碼晶元msm7702 - 3為核心構建了數據處理主板和以單片機為控制器的撥號顯示子板組成。數據處理主板的核心任務，包括語音數據處理、以太網幀處理、協議處理、呼叫處理等。撥號顯示子板則完成通話前的顯示用戶所撥過的ip地址，通話期間網路狀態的顯示等等。
  7. The fifth chapter expatiate the resolve method of false code during the video processing. the emphasis is put on the false code resolve method in video post - processing. these methods are adopted in many video processing chips include sti5518

    闡述了對于視頻處理過程中誤碼的解決方法，著重對于視頻后處理過程的誤碼檢測和掩蓋方法進行了說明，這些方法也是現行解碼晶元普遍使用的誤碼解決方案。
  8. The software controls the signal generator, which makes the brightness can be tracked. the software also controls the 12c bus interface. by setting the lcd tv ' s decoder, the software adjusts the white balance of the lcd tv

    白平衡系統的軟體控制白場信號發生器使得亮度可以自動跟蹤，軟體對cm - 7l送來的數據進行計算處理，並且根據處理的結果對i ~ 2c總線操作，修改液晶電視機內部解碼晶元中的數據達到白平衡調整的目的。
  9. Introduces operation principle and interface circuit design of video codec adv611. 3

    介紹了新一代視頻編解碼晶元adv611的工作原理和介面電路設計。
  10. On designing of the encoder, by using the decoding for video chip saa7113 made in philips, analog video signal inputted realizes a / d conversion in analog / power block

    編碼器的設計中，模擬/電源塊主要實現的功能是對輸入的模擬視頻信號進行a / d轉換，解碼晶元採用philips公司saa7113 。
  11. Chapter 3 presents the design and implementation of memory management of rtos for the hdtv integrated source decoder chip

    第三章具體描述應用於hdtv信源解碼晶元的實時操作系統存儲管理策略的設計及實現。
  12. Digital - video encode - decode chip, one of the basic components of digital - video devices, is still relying on import products

    數字視頻解碼晶元是數字電視等視聽設備的核心器件，目前絕大多數仍依賴國外進口。
  13. In this paper, the first chapter gives an overview of hdtv, and then talks about the technology involved in asic

    本文第一章緒論首先概述了數字高清晰度電視，引入了數字高清晰度電視通道解碼晶元的基本概念。
  14. In this dissertation, the design and implementation of a soc - based real - time operating system, named iota, has been presented

    本文以hdtv信源解碼晶元為soc原型，設計並實現了一個基於soc的實時操作系統iota 。
  15. In this thesis, we research and implement me memory management methods of rtos for the hdtv integrated source decoder chip

    本文以hdtv信源集成解碼晶元為開發背景，研究和實現了應用於該soc晶元的實時操作系統的存儲管理策略。
  16. This paper focuses on principles of the controller in dtv ( digital television ) channel receiving chip and its realization in asic

    本文著重於有線視頻廣播傳輸系統中通道解碼晶元的控制部分的基本原理及其在專用集成電路晶元（ asic ）上的具體實現。
  17. This paper describes the error control coding of the flex paging system, with emphasis on the design and implement of the flex decoder circuit by means of the fpga technology

    本文介紹了flex高速無線尋呼系統中的差錯控制編碼技術，以及bch （ 32 ， 21 ）糾錯碼的構成和譯碼方法，重點討論了flex高速尋呼解碼晶元的fpga設計與實現。
  18. This paper is to discover the clamp circuits for realizing video decoder ic ( integrated circuit ), and focusing on realizing the function of video clamp circuit and project design with cmos process

    本文旨在探索為實現視頻解碼晶元的模擬前端而作的箝位電路設計。重點論述了在cmos工藝下視頻箝位電路的功能實現及設計方案。
  19. The application of hardware decoding circuit is widely, because it not only can be used on computer, but also can be used on consumer equipment like digital - tv and dvd - player. the avs and h. 264 standards and the architecture of digital video decoder chip are investigated in the thesis, and a high - definition multi - mode decoder soc chip is proposed. the chip can support avs level 4. 0 / 6. 0 and h. 264 main profile level 4. 0

    本文在研究了avs和h . 264視頻編碼標準和數字視頻解碼晶元系統結構的基礎上，設計了同時支持avs和h . 264的高清解碼soc晶元，能夠對avslevel4 . 0 / 6 . 0和h . 264mainprofilelevel4 . 0的高清晰度視頻碼流實時解碼。
  20. Moreover, video control program to implement internal function of fpga is designed including video capture time sequence control, ping - pang frame buffer read and write time sequence control and lcd display time sequence control, and program ' s simulation and analysis is also provided. at last, this paper presents a portable iv ' s video processing system, and proposes three buffer strategy to control capture buffer. and a moving object detection algorithm of combing an adaptive background subtraction technique with a three - frame differencing is adopted

    設計了基於fpga系統結構的車載視頻顯示電路板；利用單片機io口模擬i2c時序，實現了視頻解碼晶元控制；利用fpga實現視頻控制，研究了採集通道時序控制、雙幀存ram讀寫時序控制及lcd顯示時序控制的方法，並進行了軟體模擬和分析；設計了車載視頻檢測系統方案，給出了管理採集緩沖區的三幀緩沖策略，採用綜合三幀差分和自適應背景相減的演算法實現運動檢測，連通體檢測去除虛目標，模擬實驗證明其有效性，同時分析了該演算法在dsp視頻檢測系統中的簡單實現方法。
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