觸發信號鐘 的英文怎麼說

中文拼音 [chùfāxìnháozhōng]
觸發信號鐘 英文
triggered time clock
  • 觸 : Ⅰ動詞1 （接觸） touch; contact 2 （碰; 撞） strike; hit 3 （觸動） touch 4 （感動） move sb ; sti...
  • 發 : 名詞（頭發） hair
  • 號 : 號Ⅰ名1 （名稱） name 2 （別號; 字） assumed name; alternative name3 （商店） business house 4 （...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 觸發 : detonate by contact; touch off; trigger; strike
  1. This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution

    主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。
  2. Furthermore, low power flip - flop design by reducing the short - circuit power which relates with clock overlapping is also mentioned in this paper

    此外，由於觸發器的短路功耗和控制觸發器的時鐘信號的交迭程度有關，因此文章還對通過合理規劃時鐘信號的交迭來達到減少觸發器短路功耗的低功耗觸發器結構進行了討論。
  3. Triggered time clock

    觸發信號鐘
  4. Based on the system clock and trigger input signals, using fpga to generate trigger output signals in given working modes

    3 .通過fpga實現在一定系統時鐘和觸發信號作用下各種工作模式的觸發信號的產生。
  5. In the time - domain, based on the principle of random sampling of dso. two way ( " time amplifing in dual slope integral " and " time - voltage convert " ) are implemented to measure the time between the system triger and writing clock. thus random sampling interpolate can be done to measure repeated signal in high frequency with the a / d convert and controller which frequency are lower

    在時域，根據數字示波器隨機取樣原理，用兩種方法（雙斜率積分時間放大測量方法和時間? ?電壓轉換測量方法）測量數字示波器系統觸發和采樣寫時鐘間時間間隔，用低速a / d轉換器及控制器進行模?數轉換和控制，以此進行隨機取樣內插，從而實現了對高頻率重復信號的測量。
  6. According to the redundancy in digital circuits, we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits. to erase the redundant transition of the clock, the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design

    為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計並應用於時序電路設計中。
  7. In this paper, low power flip - flops designs by the reduction of the load of clock or the data path ; by the reduction of clock swing ; by the reduction of clock frequency and by the reduction of those idle transitions in cmos circuits with clock gating are discussed

    與此相對應的，在本論文中，分別對將少時鐘負載或數據通路的負載的觸發器設計；減小時鐘信號幅度的觸發器設計；降低時鐘頻率的雙邊沿觸發器設計以及應用門控技術來減少觸發器無效跳變設計的觸發器結構進行了討論。
  8. In this paper, the method of in - bore abnormal phenomenon remote detecting is presented. considering of the multi - channel transient signals automatic acquisition, a project of pcm signal hardwire transmission data automatic acquire system is put forward. in this system, a pcm demodulate board is designed, it can decode the pcm code string which contain the information of the multi - channel transient signals, it also can catch the useful data automatically, and transmit these data to upper pc by rs485

    在該系統中，為了能夠解調出包含多路動態信號數據的高碼速率pcm信號，設計並製作了一種適用的pcm解調板，能夠從pcm碼流中恢復出位時鐘信號，從而與發送端保持位同步和幀同步，從而對pcm碼流可靠地解調、緩存，並能根據計算機設定的觸發條件自動地捕獲多路信號的有效段，然後利用rs485總線將這些數據可靠地遠傳至計算機以供顯示、分析和保存。
  9. The content of fpga is downloadable via prom, jtag or the special port on chip by xilinx software. the module can delay input signals from 0ns to 1. 8us stepping by 25ns. it ' s precision is 25ns

    插件經過測試，能在0 71時鐘周期之間，以一個時鐘周期為步長實現對輸入信號的可編程延遲，延遲精度為25ns ，滿足觸發判選系統總觸發邏輯對齊來自各個探測器觸發子系統信號的要求。
  10. Based on the construction of traditional flip - flop, we propose a novel edge - triggered flip - flip using one latch controlled by narrow pulse according to race - hazard of clock. then this principle is adopted in ternary circuit, a new ternary d type edge - triggered flip - fiop based on cmos transmission gate is proposed

    在二值單閂鎖結構邊沿觸發器的基礎上，把利用時鐘信號競爭冒險的思想應用於三值電路中，提出了基於cmos傳輸門的二值d型時鐘信號競爭型邊沿觸發器。
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