譯碼線 的英文怎麼說

中文拼音 [yìmǎxiàn]
譯碼線 英文
decoding line
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  1. Bcd detail specification for electronic component. semiconductor integrated circuit. type ch2019 4 - line to 10 - line decoder with bcd - in

    電子元器件詳細規范.半導體集成電路ch2019型4線- 10線譯碼器
  2. Small systems use partial or linear decoding to select the memory.

    小系統使用局部譯碼或線選譯碼來選擇存貯器
  3. Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design

    Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。
  4. 4 di c, proietti d, telatar i e et al. finite - length analysis of low - density parity - check codes on the binary erasure channel. ieee trans

    如果停止距離較小， ldpc碼在迭代譯碼下的錯誤概率曲線經常會出現所謂的"地板效應error floor 。
  5. Cascaded low - density erasure codes are based on sparse random bipartite graphs. very efficient linear time encoding and erasure recover algorithms with the arbitrarily near erasure channel capacity performance of the codes with respect to the algorithms have made them one of the most optimal coding techniques up to now

    基於稀疏隨機二部圖的級聯型低密度糾刪碼因其線性時間的編譯碼演算法和可任意逼近刪除通道容量限而成為目前最佳編碼技術之一。
  6. In this paper, the common used encoding algorithms and basic finite - field opera - tions algorithms are introduced, and the decoding algorithms such as inverse - free ber - lekamp - massey ( ibm ) algorithm, reformulated inverse - free berlekamp - massey ( ribm ) algorithm and modified euclidean algorithm are analyzed in great detail. based on the ribm algorithm, a modified structure and a pipelined decoder scheme are presented. a tradeoff has been made between the hardware complexities and decoding latency, thus this scheme gains significant improvement in hardware complexity and maximum fre - quency

    本文簡要介紹了有限域基本運算的演算法和常用的rs編碼演算法，詳細分析了改進后的euclid演算法和改進后的bm演算法，針對改進后的bm演算法提出了一種流水線結構的譯碼器實現方案並改進了該演算法的實現結構，在譯碼器復雜度和譯碼延時上作了折衷，降低了譯碼器的復雜度並提高了譯碼器的最高工作頻率。
  7. There are many decoding schemes for convolutional code, such as sequence decoding algorithm, fano algorithm, viterbi algorithm. but in fact, what ' s used widely is viterbi decoding algorithm. the viterbi decoding algorithm, proposed in 1967 by viterbi, is a decoding process for convolutional codes in memory - less channel, which takes full advantage of convolutional codes. since viterbi algorithm is proposed, it has obtained rapid development whether in theoretics or in practice and been applied to all kinds of data transmission systems, especially to digital wireless communications and deep space communications

    卷積碼的譯碼演算法方案有很多，如序列譯碼演算法、 fano演算法、 viterbi演算法，但是真正大規模應用的還是viterbi演算法。 viterbi譯碼演算法是1967年viterbi提出的，它是一種對無記憶通道卷積碼進行譯碼的演算法。它充分發揮了卷積碼的特點，因而自viterbi演算法提出以來，無論在理論上還是在實踐上都得到了極其迅速的發展，並廣泛的應用於各種數據傳輸系統，特別是無線通信和衛星通信系統中。
  8. An engineer case is introduced, which is " the identification of coke oven sequence number and distant transmission of pushing coke information ". advanced technology of wireless data transmission and computer control is adopted to improve pushing coke motor. the data transmitter - receiver is introduced in the engineer case, and the improved step - by - step decoding algorithm is put into practice

    在此系統中對推焦車採用較為先進的無線遠傳技術和計算機控制技術進行改造，選用深圳「友迅達」的數傳電臺fc - 201 e開發了「推焦過程信息遠程傳輸系統」 ，並將本文提出的這種改進的step - by - step譯碼演算法應用其中，實現推焦車上的推焦過程監測儀和上位機以及其他現場執行機構的可靠、有效的通訊。
  9. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。
  10. When the number of the antennae is not changed, the complexity of sttc decoding would increase on index with the acceleration of the transmission rate

    空時格形碼在天線數目固定時，譯碼復雜度隨發射速率的增大呈指數增加。
  11. Improve on algorithms can enhance encoding / decoding performance. with pipeline and systolic array architectures adopted in the hardware implements, encoder / decoder based on fpga can work better

    對編譯碼演算法的改進有助於提高rs編譯碼器的性能，而利用fpga來實現rs編譯碼器，並採用流水線、心縮式陣列等優化結構，更能提高編譯碼器的性能。
  12. Although they are not shown in this diagram, there would be control lines from the instruction decoder

    盡管圖中沒有顯示，但指令譯碼器還有下列功能的控制線。
  13. The company beijing cyber - video communication technology co., ltd. offers services from the ranges multiplexer, decoder in addition to embedded

    公司專業從事單線、譯碼機以及衛星接收機和語言、通話業務。
  14. Since their rediscovery, design, construction, decoding, analysis and applications of ldpc coded have become focal points of research. among them, the decoding algorithm and its implementation design are the focus of this thesis

    Ldpc碼是一種具有稀疏校驗矩陣的線性分組碼，研究結果表明，採用迭代的概率譯碼演算法， ldpc碼可以達到接近香農極限的性能。
  15. This class of codes decoded with soft - in soft - out ( siso ) iterative decoding performs amazingly well. since their rediscovery, design, construction, decoding, analysis and applications of ldpc coded have become focal points of research

    Ldpc碼是一種具有稀疏校驗矩陣的線性分組碼，研究結果表明，採用迭代的概率譯碼演算法， ldpc碼可以達到接近香農極限的性能。
  16. This paper describes the error control coding of the flex paging system, with emphasis on the design and implement of the flex decoder circuit by means of the fpga technology

    本文介紹了flex高速無線尋呼系統中的差錯控制編碼技術，以及bch （ 32 ， 21 ）糾錯碼的構成和譯碼方法，重點討論了flex高速尋呼解碼晶元的fpga設計與實現。
  17. The statistical characteristic of extrinsic information from component decoders is discussed. based on it, ? it is explained that the related curves of input - output snr could be used to measure the performance and convergence of iterative decoding ; ? two types of turbo iterative stopping criteria are designed ; ? the methods to updating snr estimation in the process of iterative decoding is provided ; ? a way to implement synchronization of carrier phase by serial concatenation scheme is devised

    在分析迭代譯碼輸出外部信息的統計特性基礎上?考察了迭代譯碼器輸入輸出snr關系曲線，並說明它可以作為衡量迭代譯碼性能和收斂性的工具； ?設計了兩類新的turbo迭代譯碼停止準則； ?提出了在迭代譯碼過程中更新snr估計的方法；國防科學技術大學研究生院學位論文設計了利用外部信息統計量實現載波相位同步的串列級聯方案。
  18. Chapter 5 gives the design illumination of the rs coder and decoder based on fpga. then it gives the integrated results for realization design of the rs ( 31, 15 ) error - correcting code. after that, it gives the functional and layout simulation results for the limited field multiplier, divider, rs coder and rs de - coder

    第五章給出了基於fpga實現的rs編碼器和譯碼器設計說明， rs （ 31 ， 15 ）糾錯碼設計實現的綜合結果，有限域乘法器、除法器、 rs編碼器、 rs譯碼器的功能模擬和布局布線后模擬結果，最後總結主要的調試經驗。
  19. Erasure codes which belong to standard classes of rs codes and their erasure correcting principles are introduced with emphasis on cascaded low - density erasure codes with linear time encoding and erasure recover algorithms. the encoding and decoding complexities of these codes are analyzed. 2

    介紹了標準的rs碼類糾刪碼及其糾刪原理，重點介紹了具有線性時間編碼和恢復演算法的漸近好碼?級聯型低密度糾刪碼，分析了這幾類糾刪碼的編譯碼復雜度； 2
  20. In detail, they are bit - interleaved coded modulation ( with iterative decoding ), low - density parity - check codes and stf technology. by the performance analysis of bicm ( - id ), which can make code and modulation optimal separately, and achieve maximum possible coding diversity as well as modulation gain, guidelines for its design and an easy algorithm for siso are proposed. design of capacity - approaching of ldpc codes and efficient encoding of them as well as several kinds of its decoding algorithms are investigated

    具體的講，就是討論了基於比特交織的編碼調制技術，並給出了映射方式的設計準則以及核心模塊siso的一種簡單的f - map演算法；研究了編碼最小漢明距隨碼長線性增加的ldpc碼的幾個方面的問題，包括接近香農限碼子集的度分佈對的設計、有效編碼器的實現和各種譯碼演算法的優缺點，並對基於ldpc碼的bicm應用於ofdm傳輸系統中的性能進行了模擬。
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