輸入邏輯 的英文怎麼說

中文拼音 [shūluó]
輸入邏輯 英文
input logic
  • : Ⅰ動詞1 (運輸; 運送) transport; convey 2 [書面語] (捐獻) contribute money; donate 3 (失敗) l...
  • : Ⅰ動詞1 (進來或進去) enter 2 (參加) join; be admitted into; become a member of 3 (合乎) conf...
  • : Ⅰ動1. (巡察) patrol 2. [書面語] (遮攔) blockⅡ名詞1. (巡察) patrol 2. [書面語] (山溪的邊緣) edge
  • : Ⅰ動詞(編輯; 輯錄) collect; compile; edit Ⅱ名詞(整套書籍、資料的各個部分) part; volume; division
  • 輸入 : 1 (從外部送到內部) import 2 [電學] input; entry; entering; in fan; fan in; 輸入變壓器 input tra...
  • 邏輯 : logic
  1. The parallel form of the input sequence is decoded by means of a logical decoding circuit.

    此并行形式序列通過解碼電路
  2. The system comprises three modules : the first is the ccd driver module, which controlled with cpld. programming the cpld to produce ccd driving pulses and synchronized communication signals. after preprocessing, the output video signals are transmitted into high resolution adc module, in which they are converted into digital signals, and then processed in arm processing module

    整個系統分為三個模塊: ccd驅動模塊的核心是一片復雜可編程器件( cpld ) ,對其編程產生ccd的驅動脈沖及同步控制信號;視頻出信號經預處理后,由高精度ad轉換模塊進行采樣,將ccd出的模擬信號轉換成數字量;最後,將數據送arm處理系統中進行后續處理。
  3. The merits of the inclusion of quantitative methods based on logical empiricism for explicit definition of input errors and uncertainty, approaches to quantisation of input data, and optimisation of outputs are contrasted with soft systems approaches that incorporate more linguistic and information theory into landscape analysis

    的錯誤和不確定,的數據的量子化的方法和出的最佳化的明白定義以合乎的經驗主義為基礎的數量方法的包含的功績與將較多的語言學和傳播理論納風景分析的軟性系統方法一起對比。
  4. Physical units transmit information to and from the microcomputer via appropriate interface logic.

    各種實體設備能夠通過適當的介面電路對計算機傳出)信息。
  5. The structure includes : iicm ( input interface control module ) 、 oicm ( output interface control module ) 、 edcm ( experiment data control module ) 、 sefcm ( simulation experiment framework control module ) 、 mscm ( model structure control module ) 、 slcm ( simulation logic control module )

    其中包括:介面控制、出介面控制、實驗數據控制、模擬實驗框架控制、模型結構控制以及模擬控制。
  6. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼; fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的控制;視頻數據幀存模塊為大量高速的視頻數據提供緩沖區;基準時鐘產生模塊通過基準視頻信號為系統提供精確的相關同步信號; d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用: i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  7. Several semi - active control algorithms used in the semi - active suspension system with mr dampers are proposed and developed including the " on - off " voltage controller, the continuously linear variable voltage controller, the modulated continuously linear variable voltage controller based on " sky - hook " damping concept and the hybrid controller based on the combination of " sky - hook " damping concept and " ground - hook " damping concept and the fuzzy logic controllers using measurements of the relative displacement between the sprung and unsprung mass or the absolute acceleration of the sprung mass as the input variables of fuzzy logic controllers. the simulation models were prepared in matlab ? simulink ? fuzzy toolbox programs. the experiment setup of the semi - active suspension system with mr dampers in the lab has been designed and developed

    根據磁流變阻尼器特性和對懸架系統動力學特性的規律性研究,為磁流變阻尼器設計了基於「天棚」阻尼控制概念的「 on - off 」 、線性連續和修正的線性連續控制策略,基於「地棚」阻尼控制概念的磁流變阻尼線性連續控制策略, 「天棚」阻尼和「地棚」阻尼控制概念線性組合起來的磁流變阻尼混合控制策略,根據模糊控制原理設計了以簧載質量和非簧載質量間相對位移或簧載質量加速度分別作為變量的模糊控制器用於磁流變阻尼半主動懸架的智能控制。
  8. So here introduces a new method - the combination of boundary scan with deltascan, in which deltascan is applied to do short and open test in ict, so that the number of vectors used to test circuit short and open in boundary can be eliminated. all vector test, including boundary scan test, need to create test vectors

    任何元件的矢量測試,包括邊界掃描測試,都必須先生成測試矢量,然後用這些測試矢量作為端的激勵信號,因此測試矢量是矢量測試的基礎,測試矢量生成方法的難易程度和測試矢量數目是邊界掃描技術能否在實際中應用的關鍵。
  9. The hardware has two input channels of high - speed analog signal, with the signal amplitude of 0 - 5v, the conversion precision of 12bits, and the maximum sampling rate of 400ksps. this system includes 4 dsps ( adsp 2181 ), which can be arranged as a pipe line processing array. many algorithms can be realized in this system

    系統硬體有兩路模擬數據採集通道,模擬信號范圍為0 ? 5v ,轉換精度為12位,最高采樣率400ksps ;系統包含4片dsp ( adsp2181 )構成的流水線型的處理陣列,可用於實現各種演算法;系統的控制由fpga完成。
  10. The plug - in cards provide dual form - c relays, quad form - a, or either quad sinking or quad sourcing open collector logic outputs

    式插件提供兩芯form - c繼電器5a四芯form - a繼電器3a或者陷流和源流集電極開路出。
  11. The hardware in this system includes a digital signal processor, an analogy input channel, a lcd, an analogy output path, a keyboard input part, a guard circuit and a logic control circuit

    該系統硬體包括數字信號處理器晶元、前向通道、液晶顯示器、模擬量出部分、鍵盤部分、保護電路部分和控制部分。
  12. Digital circuit includes two kinds - the assembly logic circuit and the sequential logical circuit, the characteristic of the assembly logic circuit is that the output signal is only the function which enters the signal and has nothing to do with the entering state at any other moment, it has no function of memory

    摘要數字電路分為組合電路和時序電路兩類,組合電路的特點是出信號只是該時的信號的函數,與別時刻的狀態無關,它是無記憶功能的。
  13. Electricity meters - specification for input and output switching or logic arrangements for multi - rate registers for electricity meters

    電度表.第5部分:多費率記數器出開關或電路規范
  14. Many mature technologies on this level have been brought out, such as the relational algebra law, the improved logical query plan, the cost estimation of operation, the selective plan based on cost and order of joint, etc. although many methods have been tried out, no remarkable result or noteworthy technology has come to reality because of complexity of data decomposition and network effects

    例如,從物理查詢計劃的底層磁盤出到語法分析階段的語法分析樹、用於改進查詢計劃的代數定律、查詢計劃的改進,以及操作代價的估計、基於代價的計劃和連接順序的選擇等全過程,都進行了不懈的努力。在這方面的研究已經非常成熟。
  15. Explains how to enter text, numbers, dates, or logical values

    解釋如何文本、數字、日期或值。
  16. The tester sets the inputs to all combinations of 1 ’ s and 0 ’ s and looks for the correct logic values on the outputs

    測試設備對設置連續的1和0 ,檢測出端的正確值。
  17. During that short period, the tester must also capture the output value of the ic

    在這個過程中,對端施加一個短時的比值高的電流,同時測試儀器要捕捉到集成電路的出值。
  18. Standard logic cells, memory design and io layout design

    標準單元,存儲電路設計及出單元版圖設計。
  19. This is normal since you have to type the logic

    這是正常的,您必須輸入邏輯
  20. Then, the rtl design of the module about contol transfer is emphasized. it mainly includes the out logic function, the in logic function, the special logic function and the configuration logic function

    然後從模塊的演算法級設計的角度,著重討論了控制傳模塊端點0的設計,主要包括功能塊、輸入邏輯功能塊、特殊功能塊和配置功能塊。
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