輸出寄存器 的英文怎麼說

中文拼音 [shūchūjìcúnqì]
輸出寄存器 英文
output register
  • 輸 : Ⅰ動詞1 （運輸; 運送） transport; convey 2 [書面語] （捐獻） contribute money; donate 3 （失敗） l...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 輸出 : 1 （從內部送到外部） export 2 [電學] output; outcome; outlet; out fan; fanout; 輸出變壓器 output ...
  1. All nominal outputs of the shift register are 1.

    移位寄存器的全部「原」輸出都為1。
  2. Applying two perpendicular polarized light states and a no - light state to express information, this new theoretical system covers : a ) whole architecture constructed from light processing, light transmission, electric control and photoelectric input and output ; b ) various computing units mainly consist of liquid crystal element and polarimeter ; c ) light bus mainly consists of interlinkage optic valves ; d ) ternary memory formed from semiconductor memory ; e ) register formed from optic fiber ring ; and i ) huge - numeral management based on the new concept of calculating path and calculating channel

    這個理論包括：光處理、光傳送、電控制、綜合輸入輸出的總體結構；以液晶元件和偏振器為主的各類運算器結構；以互連光閥為主的光空間總線；以半導體存儲器為主的三值數據存儲器結構；以光纖環為主的寄存器結構；以算位、算道新概念為基礎的巨位數管理方案等。
  3. All nominal outputs of the shift register are 1

    移位寄存器的全部「原」輸出都為1 。
  4. In chapter 4, the circuit of the carrier synchronization unit is implemented on fpga, the resistor transistor logic ( rtl ) schemes are presented

    第四章在fpga平臺上實現載波同步單元電路，並給出了實現后的fpga資源消耗、寄存器傳輸邏輯（ rtl ）原理圖。
  5. Also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals

    搭建了一個驗證系統，通過單片機來配置初始化寄存器和控制寄存器的值來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。
  6. It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function

    本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。
  7. In this paper, we discuss a kind of filter generator whose filter functions have less input bits than the degree of the linear feedback shift register ( lfsr ). by analyzing the structure of the filter generator and its equivalent system, we give out a conditional search algorithm ( csa ) to attack this kind of filter generators

    針對濾波函數f （ x ）的輸入比特數m少於線性反饋移位寄存器級數n的濾波生成器，本文通過分析其等價的組合生成器的結構，以及不同節拍上驅動序列的各個符號之間的制約關系，給出了廣義解序列的概念，並提出了類似遍歷二叉樹的條件搜索演算法csa ，用於攻擊該類特殊的濾波序列。
  8. Chapter five discusses the design and the process of the generation of the control function, including counter, accumulator, comparator, shift register, demultiplexer, collector, access record. chapter six gives some advice and opinions on how to improve this computer software

    其次介紹了計數器、累加器、比較器、多路輸出選擇、移位寄存器控制項；數據類中的收集器、訪問記錄/部分輸出記錄等控制項的功能介紹和編程思路以及使用實例第六章對平臺的完善和改進闡述了一些個人的建議和想法。
  9. Within this scope, users can get almost any frequency clock by configuring the register, as the tune - process is nearly continual ( in fact there are many discrete frequency points ). the main circuit of the clock generator is a cppll ( charge pump pll ) designed in a method

    該時鐘發生器可以向系統提供頻率范圍是93 . 75k - 180mhz的時鐘信號，用戶可以通過配置寄存器的方法使時鐘發生器輸出自己需要的頻率，而且這一調頻過程幾乎是連續的（實際上是眾多離散點構成的線性近似） 。
  10. A research is done for studying the reusable design principles of bus function model ( bfm ) and bus monitor for reusability. the functional verification framework is proposed in this dissertation can be apply in soc system level, rtl level and gate level verification. we accumulated experiences to soc functional verification

    討論了功能驗證平臺中總線功能模型（ busfunctionmodel ， bfm ）和總線監視器（ busmonitor ）的設計方法，給出了可重用設計的規則；本論文建立的soc功能驗證系統結構，可以應用於較大規模的soc的系統級、寄存器傳輸級和門級的驗證中，通過本課題研究，為國內soc功能驗證積累經驗，為國家超大集成電路的發展奠定一個堅實的基礎。
  11. Making use of the powerful capabilities of the pci chip, high - speed data of the dsp platform are transferred both ways at dma mode, and low speed data such as initialization and configuration information are transferred at direct slave mode. this paper shows in detail the workings of pci9054, the configuration of its control register, and the writing of platform driver with api functions provided by the manufacturer

    利用pci介面晶元的強大功能，本文提出了採用dma模式雙向傳輸dsp平臺的高速數據，採用從模式傳輸初始化信息及配置信息等低速數據，並詳細介紹了pci9054的工作方式，控制寄存器的配置以及調用廠商提供的api函數編寫平臺驅動程序。
  12. With software and hardware co - design method, this paper proposes an algorithm to calculate register lifetime in programs, and the control of writing results back into rf is implemented through an enable control signal provided by instruction encoding at compile time

    基於軟硬體協同設計的思想，在研究局部變量生存期演算法的基礎上，本文提出了通過編譯器指令編碼實現對硬體結構的使能控制，即控制流水輸出結果是否寫回寄存器文件，以減少對寄存器文件的寫次數，從而降低寄存器文件埠的讀寫壓力。
  13. The configure file is downloaded into the fpga chip according to the fpga design fl ow. also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals

    使用xillinx的fpgaxc2550pq208 ，經過fpga的實現流程，把配置文件配置到xczs5opqzos ，搭建了一個驗證系統，通過單片機來對各控制寄存器寫入控制字來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。
  14. The a / d and cap circuits on dsp sample the voltage and current signals coming from the signal sampling circuit and the speed signal of the motor respectively. the " dead time " register of the dsp prevent directive - through of the igbts on the up and the down bridge arms

    利用dsp上的死區寄存器設置ipm驅動信號的死區時間防止上下橋臂igbt的直通；利用板上集成的a / d轉換器採集經過板級外圍電路處理的電路信號；利用板上的捕獲單元cap採集通過轉速計的輸出從而得到電機的轉速。
  15. Information is transmitted to and from registers via buses.

    信息是通過總線輸入寄存器或由寄存器輸出的。
  16. Analyzing every part ’ s function and characteristic, i improve overflow control unit ’ s design technique to suit fpga design and traditional register exchange survivor managing algorithm. the system use input clock as system clock and use parallel structure in system to provide flexible speed

    採用適合fpga特點的溢出控制設計方法;改進傳統的寄存器交換法re （ registerexchange ）的倖存路徑管理設計方法;全系統採用輸入數據的同步時鐘作為系統時鐘，系統內部採用全并行的方式，以提供靈活的速度。
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