輸出緩沖 的英文怎麼說

中文拼音 [shūchūhuǎnchōng]
輸出緩沖 英文
out-buffer
  • : Ⅰ動詞1 (運輸; 運送) transport; convey 2 [書面語] (捐獻) contribute money; donate 3 (失敗) l...
  • : Ⅰ形容詞1 (遲; 慢) slow; unhurried 2 (緩和; 不緊張) not tense; relaxed Ⅱ動詞1 (延緩; 推遲) d...
  • 輸出 : 1 (從內部送到外部) export 2 [電學] output; outcome; outlet; out fan; fanout; 輸出變壓器 output ...
  1. By comparing and analyzing the advantages and disadvantages of three kinds of voltage reference circuits, type of current density ratio compensation 、 weak inversion type and type of poly gate work function, a cascode structure of type of current density ratio compensation is chosen to form the core of voltage reference circuit designed in this paper. applying the negative feedback technology, an output buffer and multiply by - 2 - circuits are designed, which improve the current driving capability

    然後通過比較和分析電流密度比補償型、弱反型工作型和多晶硅柵功函數差型三種帶隙電壓基準源電路結構的優缺點,確定了電流密度比補償型共源共柵結構作為本設計核心電路結構,運用負反饋技術設計了基準輸出緩沖電路、電壓倍乘電路,改善了核心電路的帶負載能力和電流驅動能力。
  2. Every column in sensor array work in parallel and have their own cds noise reducing circuit. the signals after fpn reducing are output from the output buffer amplifiers

    傳感陣列中各列感光單元的傳感信號并行,分別由對應的相關二次采樣電路進行降噪處理,去除固定模式噪聲后的信號通過輸出緩沖放大電路進行
  3. This paper presents a theoretic analysis of the temporal characteristics of output buffer in switch, gives the probability distribution function of delay and average queuing time, and compares the end - to - end delay between traditional and switched ethernet. vlan is one of important technologies that switch has to implement. switch has to rapidly and efficiently find and maintain an un - looped topology

    在建立交換機的延遲模型基礎上,推導輸出緩沖延遲分佈、隊列大小等特性;接著比較傳統總線型以太網和交換式以太網的端到端延遲,為交換機以及交換式以太網的設計和分析提供可靠的理論基礎。
  4. Ibis 3. 2 electronic design automation libraries - part 1 : input output buffer information specifications ibis version 3. 2

    電子設計自動化程序庫.第1部分:輸出緩沖器信息規范
  5. Electronic design automation libraries - part 1 : input output buffer information specifications, version 3. 2

    電子設計自動化圖書館.第1部分:輸出緩沖信息規范
  6. The current in the dac ’ s output can drive the load, and the structure can save a buffer consisted of operational amplifier, so the structure can achieve high speed with no close - loop and feedback in this circuit

    該10位分段式電流舵型數模轉換器的端可直接用電流來驅動負載阻抗,省去運算放大器構成的輸出緩沖,整個電路中沒有形成閉環和反饋,因此這種電路結構可以達到很高的速度。
  7. Writes a specified number of bytes to an output buffer at the specified offset

    將指定數量的位元組寫入輸出緩沖區中的指定偏移量處。
  8. Writes a specified number of characters to an output buffer at the specified offset

    將指定數量的字元寫入輸出緩沖區中的指定偏移量處。
  9. A record operation that writes all i / o buffers to a file if they haven ' t already been written

    將所有輸出緩沖器的內容寫入一個文件中的一種記錄操作。
  10. Method to flush any messages currently in the log file s output buffer

    方法刷新當前位於日誌文件輸出緩沖區中的所有消息。
  11. An output buffer amplifier used in detection circuit of micro sensor

    用於微傳感器讀電路的輸出緩沖放大器
  12. We can modify the input output part of the source code to make the tools capable of handling input output buffers rather than files

    我們可以修改源代碼的部分讓那些工具能夠處理輸出緩沖區而不是文件。
  13. The buffer _ size must be transported before the compressed data, thus the expanding program can read out the size in it. so the consistency of compression and pi expanding model can be ensured

    壓縮代碼之前先輸出緩沖區大小值,這樣解壓程序可從壓縮代碼中得到該值,從而確保壓縮與解壓模型的一致性。
  14. The following example returns current output buffer information for an assumed session id of

    的會話id返回當前輸出緩沖區信息。
  15. Buffer, input ontput

    輸出緩沖
  16. This function discards the contents of the output buffer and turns off output buffering

    輸出緩沖都關閉了,你怎麼可能還呢?
  17. In the description of circuit design, the emphasis is paid the following hardware modules : ad / da inverter, dsp module, external program / data memory, cpld control logic, serial communication module, power module, and so on. problems and the corresponding solutions found in the design and debug stage are discussed, too. finally, the low - level software driver design is presented in detail, including system booting, initialization of dsp registers, cpld logic and timing control, drivers for asynchronous communication fifo, and drivers for ad converter

    在電路模塊分析中,重點介紹了語音的入放大和輸出緩沖部分、 ad da轉換、 dsp語音壓縮解壓、外部程序數據存儲器、 cpld邏輯控制、串列收發組件、電源供電以及dsp的jtag介面等等,並且給了在硬體電路設計和調試過程中的問題與解決辦法。
  18. Input output buffer information

    輸出緩沖器資訊規格
  19. Writes data to the serial port output buffer

    將數據寫入串列埠輸出緩沖區。
  20. Flushes the output buffer, and then closes the

    刷新輸出緩沖區,然後關閉
分享友人