通用邏輯陣列 的英文怎麼說

中文拼音 [tōngyòngluózhènliè]
通用邏輯陣列 英文
generic array logic
  • : 通量詞(用於動作)
  • : Ⅰ動詞1 (使用) use; employ; apply 2 (多用於否定: 需要) need 3 (敬辭: 吃; 喝) eat; drink Ⅱ名...
  • : Ⅰ動1. (巡察) patrol 2. [書面語] (遮攔) blockⅡ名詞1. (巡察) patrol 2. [書面語] (山溪的邊緣) edge
  • : Ⅰ動詞(編輯; 輯錄) collect; compile; edit Ⅱ名詞(整套書籍、資料的各個部分) part; volume; division
  • : Ⅰ名詞1 (作戰隊伍的行列或組合方式) battle array [formation]: 布陣 deploy the troops in battle fo...
  • : Ⅰ動1 (排列) arrange; form a line; line up 2 (安排到某類事物之中) list; enter in a list Ⅱ名詞1...
  • 通用 : be in common use; be current; apply or be used universally
  • 邏輯 : logic
  • 陣列 : [統計學] array陣列處理機 array processor; 陣列印表機 array printer; 陣列雷達 [電學] array radar
  1. The hardware has two input channels of high - speed analog signal, with the signal amplitude of 0 - 5v, the conversion precision of 12bits, and the maximum sampling rate of 400ksps. this system includes 4 dsps ( adsp 2181 ), which can be arranged as a pipe line processing array. many algorithms can be realized in this system

    系統硬體有兩路模擬數據採集道,模擬信號輸入范圍為0 ? 5v ,轉換精度為12位,最高采樣率400ksps ;系統包含4片dsp ( adsp2181 )構成的流水線型的處理,可於實現各種演算法;系統的控制由fpga完成。
  2. The system uses the permanent magnet synchronous machine as the driver motor based on the idea of polygonal flux linkage locus and the permanent magnet brush - less motor is as the momentum balance motor by means of speed and current loop in order to track driver motor precisely and rapidly. the harmonious control of driver motor and balance motor is realized by making full use of the dsp hardware resource and complicated programmable logic device. the software design is composed of c and assembly language to realize motor control arithmetic of polygonal flux linkage locus

    衛星天線伺服控制系統以正弦波永磁同步電機作為驅動電機,採多邊形磁鏈軌跡法(電壓空間矢量法)的控制策略;動量平衡電機採永磁無刷直流電機,過電流環、速度環達到快速、精確跟蹤驅動電機的目的,確保了衛星姿態恆定;設計方案中充分利了dsp硬體資源和復雜實現了驅動電機和平衡電機的協調控制,並過c語言和匯編語言的混合編程實現了電機的多邊形磁鏈軌跡控制演算法。
  3. Gal : generic array logic

  4. Thirdly, to design gateway control by gal apparatus

    通用邏輯陣列( gal )器件對路控制進行設計。
  5. With the reconfigurable computing systems, the time of convolution processing is reduced to a fortieth of the computing on common pc versus without of it

    X86可重構計算系統由處理器和現場可編程組成,該系統應當稱為混合系統。
  6. < 4 > validates the designs of des / rsa on the reconfigurable system test board, and discusses the further optimized approach of the designs. the research results will be contributive to the reconfigurable computing research in the field of encryption application of our nat ion

    本課題的設計與實現以航空微電子中心的可重構計算系統為硬體環境,此系統由處理器和現場可編程組成,是混合系統,在當前一些應領域如嵌入式微處理器系統等具有非常看好的應前景。
  7. When calculate the correlation function of binary array pairs, using the boolean calculation instead of the decimal multiplication, using the method of count the number of 1 in binary integer to calculate the correlation function of binary array pairs, the speed of searching is obviously improved by these methods. by the algorithm introduced in this paper, the constant weight and normative perfect binary array pairs whose volume from 4 to 28 and quasi - perfect binary array pairs whose volume from 2 to 24 were searched and gi ved the new result

    此外,採二進制整數來表示過對整數的運算來實現偶的移位變換、完全采樣變換等運算;在計算二進偶的相關函數時,整數的運算代替十進制中的乘法運算,並計算二進制整數中1的個數的方法來計算二進偶的相關函數,以上方法的採明顯地提高了搜索速度。利上述演算法,對體積為4 28的等重規范型最佳二進偶和體積為2 24的準最佳二進偶進行了搜索,並給出了新的結果。
  8. With the fast development of the field programmable gate arrays ( fpga ), the pci ipcore has been offered by a great many manufactories, and then the engineers can integrate the users ’ logic and pci ipcore into the fpga chip, thus the simulations and the verifications of the user ’ logic can be done in the top level. so the engineers can develop pci productions with using ipcore much faster than using special chip of pci interface, and also can shorten debug periods, highly advance the integration of the pcb board

    隨著fpga (現場可編程門)技術的快速發展,很多製造廠商都開始提供pci介面核( ipcore ) ,設計者可以將pci和pci核集成到fpga裏面,並且可以在頂層過模擬來驗證pci介面以及設計的正確與否,這樣較之使那些pci專介面晶元,使ipcore就可以大幅度的提高調試速度,縮短開發周期,提高電路板的集成度和系統的性能。
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