邊界掃描 的英文怎麼說

中文拼音 [biānjièsǎomiáo]
邊界掃描 英文
boundary scan
  • 邊 : 邊Ⅰ名詞1 （幾何圖形上夾成角的直線或圍成多邊形的線段） side; section 2 （邊緣） edge; margin; oute...
  • 界 : 名詞1 （相交的地方; 劃分的界限） boundary 2 （一定的范圍） scope; extent 3 （按職業、工作或性別等...
  • 掃 : 掃構詞成分。
  • 描 : 動詞1. （照底樣畫） copy; depict; trace 2. （在原來顏色淡或需改正之處重復塗抹） retouch; touch up
  • 邊界 : boundary; frontier; border; borderline; edge range line; periphery
  1. After tested, this controller has a correct function, accord with design request and has some advantages such as plus and play, doesn ’ t need extern power, easy connection, and so on

    調試結果表明，邊界掃描控制器功能正常，符合設計要求，具有即插即用、無需外部供電、連接簡單可靠等優點。
  2. Firmware design for the boundary - scan tester

    邊界掃描測試儀的固件設計。
  3. Standard test access port and boundary scan architecture

    標準測試存取口及邊界掃描體系結構
  4. Application of boundary scan technique to the design for board - level test

    邊界掃描技術在板級可測性設計中的應用
  5. The article also addresses the mechanism of vector creation for boundary scan

    本文進一步分析了邊界掃描測試矢量生成機制。
  6. Boundary scan aims at the test of application system, e. g. pcb test

    邊界掃描測試是針對晶元的應用系統進行測試的，如pcb板測試。
  7. As a kind of new developing bit technology, boundary scan technology is widely used in industry

    邊界掃描技術作為一種新興的bit技術，在工業界內得到了廣泛的應用。
  8. A plan of design for test based of boundary scan testing is introduced for this signal processing system

    接著，提出了該信號處理系統基於邊界掃描的可測性設計方案。
  9. International standard ieee 1149. 1 describes the basic circuit structure and performance of boundary scan

    國際標準ieee1149 . 1規定了邊界掃描的基本電路結構和功能。
  10. Jx5 microprocessor ’ s testing structure comprises built - in self - test ( bist ), boundary scan and internal scan

    Jx5微處理器的測試結構由bist 、邊界掃描和內部掃描三部分組成。
  11. In this paper, we combine the standard modules realize the boundary scan of estarl and also expand it to the test of internal circuit. this structure can save the i / o port of the chip and simplify the testing program

    本文結合標準模塊設計實現了estar1的邊界掃描結構，並進行了擴展，應用到晶元內部測試，節約了測試i / o口消耗，簡化了測試過程。
  12. In this paper we investigate and carry out boundary scan ^ internal scan and built - in self - test three dft technologies in the embedded microprocessor estarl and get satisfying result, the fault coverage is more than 96 %

    本文針對嵌入式微處理器estar1的結構特點，研究並實現了邊界掃描、內部全掃描和內建自測試三種可測性設計技術，取得了良好的效果，故障覆蓋率達到96以上。
  13. As one of the design for testability technology, boundary scan test ( bst ) fixes boundary scan cells between the device pins and core logics. thus, the bsc acts as the virtual test probe that carries out the test stimulus and captures the test response

    作為一種結構插入的可測性技術，邊界掃描測試（ bst ）技術將邊界掃描寄存器單元安插在集成電路內部的每個引腳上，其作用相當于設置了施加激勵和觀測響應的內建虛擬探頭。
  14. The majority of the test vectors are used to check the connection of the pins of the device. those vectors for connection test can be removed from the vector base for the device under test when deltascan is applied together with boundary scan test. the total vectors are therefore eliminated

    測試矢量中大多數是用於測試引腳之間是否有短路或有引腳開路情況的，引入deltascan測試ic的引腳的開路和短路情況后，就可從xc5210 _ tq144的測試矢量集中去掉合併與短路，開路測試有關的測試矢量，進一步減少了邊界掃描所需的測試矢量。
  15. In the logic design, the fundamentals and characteristics of ieee std. 1149. 1 specification and usb protocol are introduced first of all. according to altera ’ s fpga cyclone, it analyzes the architecture and jtag instructions of boundary scan test ( bst ). then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software

    在介面邏輯設計中，首先分析ieee1149 . 1標準和usb協議，理解邊界掃描測試和usb數據傳輸的工作方式，然後針對altera公司的fpga器件cyclone ，通過分析它的邊界掃描測試結構和各種jtag指令，研究它的編程過程和編程特點，並提出設計方案。
  16. In this thesis, the boundary scan technique is discussed in detail and a boundary - scan test system based on computer is also developed. the main contents can be summarized as follows : 1. the ieee std 1149. 1 boundary scan testing standard is researched, and the mathematical description model and some basic theorems of boundary scan testing process is analyzed subsequently

    論文的研究內容及主要工作包括: 1 、對邊界掃描技術的基本理論和方法進行了分析和研究，並對邊界掃描測試過程中的數學描述模型以及邊界掃描測試的基本定理進行總結，為邊界掃描測試生成演算法的研究以及邊界掃描測試系統的開發奠定基礎。
  17. So here introduces a new method - the combination of boundary scan with deltascan, in which deltascan is applied to do short and open test in ict, so that the number of vectors used to test circuit short and open in boundary can be eliminated. all vector test, including boundary scan test, need to create test vectors

    任何邏輯元件的矢量測試，包括邊界掃描測試，都必須先生成測試矢量，然後用這些測試矢量作為輸入端的激勵信號，因此測試矢量是矢量測試的基礎，測試矢量生成方法的難易程度和測試矢量數目是邊界掃描技術能否在實際中應用的關鍵。
  18. Test access port and boundary - scan architecture

    測試存取口及邊界掃描結構
  19. On the other hand, boundary - scan technique intelligent fault diagnostic method was applied to practice. for most digital system, devices with boundary - scan architecture are broadly used. only using four line or five line to connect pc parallel port with cut tap ( test access port ), all the ptvs can be loaded to cut and all homologous prvs can be taken back to intelligent fault diagnosis system

    至於本文採用邊界掃描測試故障診斷技術，是考慮到本系統的通用性和簡潔性，因為對于大多數數字系統而言，具有邊界掃描結構的器件己廣泛應用，本文只需4條或5條信號線就能將pc機和被測邊界掃描電路連接起來，由此極大地簡化了智能故障診斷系統中為實現ptvs加載和prvs獲取而專門設計的介面板電路。
  20. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
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