邏輯單元塊 的英文怎麼說

中文拼音 [luódānyuánkuāi]
邏輯單元塊 英文
lub logical unit block
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 塊 : 名詞（古時佩帶的玉器） penannular jade ring （worn as an ornament in ancient china）
  • 邏輯 : logic
  1. This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga

    本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。
  2. One powerful abstraction of a sensor is a logical sensor, which is a unit of sensing or module that supplies a particular percept

    傳感器的一個強大的抽象是邏輯傳感器，它是提供一個對象的傳感單元或模塊。
  3. Mode, ext3 only officially journals metadata, but it logically groups metadata and data blocks into a single unit called a transaction

    方式下， ext3隻是正式記錄元數據，而在邏輯上將元數據和數據塊分組到稱為事務的單個單元中。
  4. With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit

    在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。
  5. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。
  6. The system selects micro control unit and programmable logic device as the core of controller, gsm terminal module as communication device, gps as position equipment, a / d sampling for voltage and current checking, solar battery as power supply, switch dc - dc as power voltage conversion, and so on

    以微處理單元與可編程邏輯器件為核心搭建系統控制器，選擇gsm無線通信模塊實現系統通信，全球定位系統實現水標燈定位， a d采樣與轉換實現電壓電流檢測，太陽能電池為系統供電，開關型dc - dc實現電源電壓轉換。
  7. After confirming system goal, according to overall design rule, system overall design is to carry out system overall logic structural design and software and hardware design of system ; system function design includes data to get and edit modular, data inquiry and statistics modular, overall estimetion modular, function district estimetion modular and typical cadastral parcel estimetion modular, land optimization deployment modular as well as urban land grade and evaluation modular ; database detailed design includes the design of space database and property database as well as design for the connection of space data and property data ; system application model analysis mainly explains models for intensivism degree, unit comprehensive value, land area potential, land benifit potential as well as typical cadastral parcel estimetion

    系統總體設計是在確定系統目標后，按照總體設計準則，進行系統總體邏輯結構設計及系統的軟硬體配置設計；系統功能設計包括數據獲取及編輯模塊、數據查詢統計模塊、總體評價模塊、功能區評價模塊、樣地評價模塊、土地優化配置模塊以及城鎮土地定級估價模塊等七大模塊的設計；數據庫詳細設計包括空間數據庫、屬性數據庫的設計以及空間數據與屬性數據的連接設計；系統應用模型分析部分主要對于集約度模型、單元綜合分值計算模型、用地面積潛力測算模型、用地效益潛力測算模型以及樣地潛力評價模型做出了分析解釋。
  8. A design ot portable digital oscillograph based on dsp is presented. a integrated prototype is composed of high speed data processing module by which signal is digitalized, data processing unit whose core is dsp, general controller as which cpld is used and terminal facility - - lcd

    通過高速數據採集模塊將信號數字化，以高性能數字信號處理器tms320vc5402為核心構成數據處理單元，採用高密度的可編程邏輯器件epf6016a設計儀器的系統控制單元，使用液晶顯示器做為終端顯示設備，構成一個完整的示波表樣機。
  9. With the exist of fpga chip ep1k30tc144 - 3, several hardware functions are realized in the chip, such as sample controlling logic, fifo inside, the connection circuit with pc, the connection circuit with mpu, the connection circuit with keyboard

    系統採用了fpga晶元ep1k30tc144 - 3 ，並且在晶元內集成了采樣控制邏輯，內置hfo ，上位機介面，單片機介面以及鍵盤介面等多個功能模塊，使得數據採集卡的結構大大簡化。
  10. The control system includes two modules, one named the input module which acquires data digitally, and the other, named the output module, controls the emission of the laser, the gating function of the single photon counting module ( spcm ) and the synchronization of the input and output modules. each of them uses a complex programmable logic device ( cpld ) as the core component, and is devided into three parts : the hardware circuit, the programming logic circuit and the software

    該控制系統主要包括控制單光子發射、單光子探測器、數據採集接收系統的輸出系統和數據採集系統兩個模塊，它們都採用復雜可編程邏輯器件cpld作為核心功能晶元，由硬體電路設計、晶元編程和高級軟體編程三部分組成。
  11. The vd is composed of four functional units : 1 ) the branch metrics unit ( bmu ) ; 2 ) the add - compare - select unit ( acs ) ; 3 ) the path metrics unit ( pmu ) ; 4 ) the survivor memory unit ( smu ) ; regarding the power dissipation of the viterbi decoder, the smu is the hottest spot in the viterbi decoder due to the frequent memory accesses. there are two traditional techniques for the realization of survivor memory unit in viterbi decoder - - register exchange ( re ) and trace back ( tb ) method

    這是當前開展低功耗邏輯優化的重要方面，也是本課題採用的方法。 viterbi譯碼器主要由四個功能單元組成:分支度量單元（ bmu ） ，加比選單元（ acs ） ，路徑度量存儲單元（ pmu ） ，倖存路徑存儲和輸出單元（ smu ） 。本文所做的viterbi譯碼器設計採用模塊化的設計方法，先對各個功能單元進行優化設計，然後將各個功能單元組合在一起，形成最終的譯碼器。
  12. In this article, we firstly analyze the present status of cbse mainly concerning its framework. some deficiencies are pointed out as follows : some present component frameworks focus on the service providing for the components, but the separation of interface layer and business logic layer is ignored ; components are tightly coupled with the api provided by the framework ; lacking the support for component unit testing ; lacking the support for the modularization of crossing cutting concerns

    本文首先以cbse中的框架為切入點，分析了cbse的現狀，並指出了其中一些不足之處：現有的一些構件框架僅僅強調給構件提供服務，而忽略了介面層和業務邏輯層的分離；構件依賴于特定框架的api ；缺乏對單元測試的支持；缺乏對橫切關注點（ crosscuttingconcerns ）的模塊化支持。
  13. By using simplified design, energy - saving design and other modem design methods comprehensively, combining with pc control and two - way cartridge valve technique, research and development is taken on logical cartridge unit control technique for the press, special hydraulic system of two - way cartridge valve for the press is developed, stress of the integrated block is analyzed by fem software ansys

    綜合運用簡化設計、節能設計等現代設計方法，結合pc控制和二通插裝閥技術，對橡膠壓塊機智能化邏輯插裝單元控制技術進行研究和開發，研製出橡膠壓塊機專用的二通插裝閥集成液壓系統，並利用有限元分析軟體ansys對集成塊進行應力分析。
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