邏輯模擬器 的英文怎麼說

中文拼音 [luómónǐqì]
邏輯模擬器 英文
logic simulator
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 擬 : 動詞1. （設計; 起草） draw up; draft 2. （打算; 想要） intend; plan 3. （模仿） imitate
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 邏輯 : logic
  • 模擬器 : emulator
  • 模擬 : imitate; simulate; analog; analogy; imitation; simulation模擬艙 boilerplate; 模擬電路 [電學] circ...
  1. The system comprises three modules : the first is the ccd driver module, which controlled with cpld. programming the cpld to produce ccd driving pulses and synchronized communication signals. after preprocessing, the output video signals are transmitted into high resolution adc module, in which they are converted into digital signals, and then processed in arm processing module

    整個系統分為三個模塊: ccd驅動模塊的核心是一片復雜可編程邏輯器件（ cpld ） ，對其編程產生ccd的驅動脈沖及同步控制信號;視頻輸出信號經預處理后，由高精度ad轉換模塊進行采樣，將ccd輸出的模擬信號轉換成數字量;最後，將數據送入arm處理系統中進行后續處理。
  2. Matlab / stateflow has a power function of logical management. flight manage system can be edited by stateflow with complex logical management. through the system uav can fly independently or fly by remote control. a power window to display the number and flight course is edited by matlab / gui, through the window flight control parameters and flight state can be adjusted

    利用stateflow強大的邏輯和圖形化編程功能模擬了無人機的飛行管理器，實現了自主飛行和遙控飛行的功能;利用gui用戶圖形界面建立了功能強大的人機界面，對simulink中的模擬數據進行顯示。
  3. This paper presents the logic circuit design of ccu for lx - 1164 cpu chip, for ccu, data and instructions are stored in separate data and instruction caches

    本人有幸在夏宏博士的指導下參加這一工程，承擔lx ? 1164cpu的高速緩存控制器（ ccu ）的邏輯設計和功能模擬。
  4. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  5. By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument

    本文具體給出了新型智能儀器硬體結構及實現，描述了智能儀器硬體設計細節，包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等，詳細地給出了設計原理圖和電路圖；給出了新型智能儀器的軟體設計細節，從而完成了新型智能儀器完整的軟硬體設計。
  6. The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data

    具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。
  7. However, since memory circuit is very large and dense and the growing of its size is amazing, it is unpractical to extract the logic parameter directly with simulation tools

    然而，由於存儲器單元密集和電路龐大的特點，並且存儲器的增大極為迅速，使得用模擬工具直接提取邏輯參數並不現實，存儲器的簡化迫在眉睫。
  8. Secondly, the composition and function of expander board is introduced, the paper describes a detail developing process of selecting component, design interface circuit, protract pcb with protel and design pci interface logic and user ' s logic. with ahdl and max + plus. in addition this paper discusses how to debug pci board, and give the simulation waveform and the result of debug. on the base of all functions is ture, this paper introduce the config registers and memory of bu - 61580, realize the interrupt function and communication based on mil - std - 1553b

    首先分析了擴展板的組成、功能，對pci介面邏輯和擴展板的內部邏輯進行詳細設計，並根據其資源要求進行器件選擇，然後使用protel工具進行電路板的製作。另外，本文還介紹了擴展板的調試方法，給出了邏輯模擬波形和調試結果。在此基礎上，本文闡述了協議晶元的配置方法，實現了1553b通訊擴展板間的通訊及中斷功能，達到了開發技術指標。
  9. In chapter three, the all sub - circuits including uvlo, current bias, ldo, oscillator, green mode, slop compensation, power limiting, pwm, ovp, blanking time generator, logic controller are designed and simulated. as a result, all of the sub - circuits are satisfied the requirements

    本文第三章對集成電路內各個模塊包括欠壓保護、電流偏置、 ldo 、振蕩器、綠色模式、斜坡補償、功率限制、脈寬調制、過壓保護、前沿消隱、邏輯控制電路等進行了設計與模擬，且達到了預定的設計目標。
  10. The hardware in this system includes a digital signal processor, an analogy input channel, a lcd, an analogy output path, a keyboard input part, a guard circuit and a logic control circuit

    該系統硬體包括數字信號處理器晶元、前向輸入通道、液晶顯示器、模擬量輸出部分、鍵盤輸入部分、保護電路部分和邏輯控制部分。
  11. The thesis discussed a parameter extraction program for the mosfet level1 model. in the analysis and design of circuit, at first, the thesis described the system function of the new dc - dc switching converter. then several sub - circuits of converter ic such as oscillator, over - temperature shutdown circuit, auto - restart counter circuit and control circuit were completely discussed

    在電路設計中，本文首先分析了開關電源電路的基本拓撲結構和psm調制模式，接著對開關電源變換器進行了系統的原理分析並設計了總體框圖，然後詳細設計了振蕩器電路，熱保護電路，自動重啟計數器電路和主控門邏輯等子電路並進行了功能模擬。
  12. Compared with the pid controller in the real - time experiment and off - line simulation, it shows that not only the output of system is small overshoot and rapid respond time when the logical rule controller acts, but also its control strategy is easy to be performed

    與傳統的pid控制器作用相比，離線模擬和在線實驗表明，邏輯規則控制器作用下的系統輸出不僅超調量小，響應時間快，而且控制策略簡單易行。
  13. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  14. Based on many other circuit formats, a new kind of logic - level circuit representation, called unified middle - level circuit format ( umcf ), is defined in this paper, in which some special operations on circuit related with power estimation and low power design. umcf can not only interchange circuits of different formats, but also convert circuits to hspice acceptable files, which can be used for transistor level power estimation

    本文結合多種不同的電路格式，自主定義了一種邏輯級電路的中間表示形式（稱為umcf ）和一系列極具特色的與低功耗技術相關的操作，它不但可以實現與其他多種電路格式之間的相互轉換，還可以將電路直接轉換成hspice可以接受的文件，進行晶體管級的電路功耗估計，這樣可以在公認的高精度的功耗模擬器上，對本文的結果進行有效的驗證。
  15. In the hardware, the conversion from serial port, parallel port or usb port to jtag port is realized by a cpld component, by which the volume of the emulator can be reduced and its reliability can be enhanced as well. the feature of this paper is the design of software section

    硬體部分主要採用了cpld器件來實現串口，並口， usb口到jtag口的邏輯轉換，採用cpld器件來實現此轉換功能不但減小了模擬器的體積，而且還增強了模擬器的可靠性。
  16. A testbench program is edited to simulate the behavior of the fifo. after the software simulation is accomplished, a real hardware circuit is designed to multiplex two data channels ( 1553b data channel and 1394 data channel ) according to ccsds standard. during the experiment and hardware debugging, the output logic of the fpga is checked up

    設計中，用vhdl語言對高速復接器進行行為級建模，為了驗證這個模型，首先使用軟體進行模擬，通過編寫testbench程序模擬fifo的動作特點，對程序輸入信號進行模擬，在軟體邏輯模擬取得預期結果后，繼續設計硬體電路，設計出的實際電路實現了將來自兩個不同速率的信源數據（ 1394總線數據和1553b總線數據）復接成一路符合ccsds協議的位流業務數據。
  17. Test board is produced out, software is programmed, and debug is done. running parameters and output waves are analyzed using functions of the emulator

    論文完成了目標試驗板的製作、軟體編程和調試工作，並利用模擬器的邏輯分析功能分析了系統的運行參數和輸出波形。
  18. In this paper an fault simulator for iddt testing is presented, which can detect concurrently the multi - faults. due to the subtle error among equipment manufacturing, the gate delays of circuits are not the same but range within limits. which induces the uncertainty of the waveform transforming time

    本文從故障激活的條件入手，利用五值邏輯，對瞬態電流測試中的延時變化進行波形分析和波形計算，採用並發模擬演算法，編程實現了一個iddt測試的故障模擬器。實際電路中由於製造工藝的限制，邏輯門的延時並不相同，而是在一定范圍內變化，引起波形變化的時間不確定。
  19. Considering the bad condition and the continuous noise existing in the factory, we carry out suggestion of further development of the fh ( frequency hopping ) algorithm to adapt for the demand of security and reliability of data transmission on the fieldbus. the essay researches the fh core in detail and carries out the improved link state history algorithm

    為了在長時間干擾源的條件下，實現藍牙無線的可靠傳輸，本文對藍牙的跳頻內核各邏輯控制器進行深入的研究，對lsh跳頻演算法提出改進方案，模擬結果證實了lsh跳頻改進方案是有效的。
  20. According to self - study ability of neural network, this paper designed a fuzzy neural network controller to apply in one of the post - stall maneuvers milestone70 degree angle of attack trimmed flight through train the fuzzy logic rules and membership functions of the traditional fuzzy logic controller, then we got satisfied results

    利用神經網路具有自學習能力的優勢，採用反向傳播學習演算法，通過對傳統模糊邏輯控制器中的模糊邏輯控制規則和隸屬函數有關參數進行訓練學習，設計了模糊神經網路控制器，應用於飛機的過失速機動「里程碑」之一? ? 70迎角定常飛行模擬計算，獲得了令人滿意的結果。
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