邏輯門電路 的英文怎麼說

中文拼音 [luóméndiànlù]
邏輯門電路 英文
logical gating circuit
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 門 : Ⅰ名詞1 （房屋、車船等的出入口 ） entrance; exit; door; gate 2 （形狀或作用像門的東西） switch; va...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 邏輯 : logic
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. The circuits driving the ccd and processing the video signal are implemented by means of cpld ( complex programmable logic device ) and hdl ( hardvvare description language ). the solution to solve the problem of multi - level logical competitive risks that occur in cpld circuits frequently was provided in details in the thesis

    Ccd的驅動電路和視頻信號處理電路採用cpld （可編程邏輯器件）和hdl （硬體描述語言）實現，文章對cpld電路中容易出現的多級邏輯冒險競爭情況作了專門的敘述和提出相應的解決方法。
  2. It integrates the functions of servo amplifier, dynamic operator, position transmitter and remote communication. many new functions have added to its original ones, such as the real - time logical judgment, malfunctions self - diagnosis, alarm & protection, led display, on - line setting and adjustment of functional parameter and position transmitter, power - absence data auto - protection, watchdog system protection, and the long - range communication with pc

    系統集伺服放大器、電動操作器、位置發送器及遠程網路式通信功能於一體，在保留對應部分原有功能的同時，還新增了邏輯實時判斷、故障實時監控、 led動態顯示數據、功能參數設置、掉電數據自保護、 「看門狗」電路保護、位置發送器在線調節、與遠程工控機數據通信等眾多功能。
  3. The thesis discussed a parameter extraction program for the mosfet level1 model. in the analysis and design of circuit, at first, the thesis described the system function of the new dc - dc switching converter. then several sub - circuits of converter ic such as oscillator, over - temperature shutdown circuit, auto - restart counter circuit and control circuit were completely discussed

    在電路設計中，本文首先分析了開關電源電路的基本拓撲結構和psm調制模式，接著對開關電源變換器進行了系統的原理分析並設計了總體框圖，然後詳細設計了振蕩器電路，熱保護電路，自動重啟計數器電路和主控門邏輯等子電路並進行了功能模擬。
  4. Secondly, the encoder circuit of quasi - cyclic which can realize low encoding complexity are designed and implemented. three encoder circuit are designed respectively with feed shift - registers and logic gates : sraa - based serial qc - ldpc encoder ; sraa - based parallel qc - ldpc encoder ; two - stage qc - ldpc encoder

    採用反饋移位寄存器與邏輯門設計了三個典型的編碼器電路:基於sraa電路的串列準循環ldpc碼編碼器;基於sraa電路的并行準循環ldpc碼編碼器;二階編碼電路。
  5. Thirdly, the paper researchs the application of single electron transistor and the synthesis theory of cicuit based on quantum dot cellular automata by synthesis example of quantum cellular neural network based on build schr ? dinger equation of coupling quantum dot. at last, the paper researchs digital integrated circuit design based on quantum dot cellular automata and design a 8 - bit quantum dot cellular adder by qcadsign based on a method of majority logic reducetion for quantum cellular automata, it prove this designer of 8 - bit quantum dot cellular adder is correctly

    Dinger ）方程為基礎的量子點細胞自動機電路綜合理論，本文以量子細胞神經網路為綜合實例，建立耦合量子點的薛定鄂（ schr ? dinger ）方程組，通過化簡得到類似細胞神經網路的非線性電路方程。最後研究了基於量子點細胞自動機數字集成電路設計，通過建立邏輯方程，簡化邏輯方程，並設計基於精簡qca擇多邏輯門8位加法器，並用qcadesign進行了模擬，實驗證明設計正確性。
  6. The teaching difficulty of the course of digital circuit basis mainly focuses on some knowledge of components, for example, semiconductor basis, separation and integration logic gate circuits

    摘要《數字電路基礎》課程的教學難點主要集中在半導體基礎、分立和集成邏輯門電路等元器件知識部分。
  7. Finally the module is accomplished successfully after installation and debugging. it mainly consists of the minimum system of dsp, a / d conversion circuit, cpld control logic, watchdog circuit, op amplifier and filter circuit

    該模塊主要由數字信號處理器最小系統、模數轉換電路、復雜可編程邏輯器件控制邏輯、看門狗電路、運算放大器電路和模擬濾波器電路構成。
  8. The output signal can then be amplified ( possibly with a logic gate at this point ) to drive the converters

    電路輸出的信號需要放大后再使用（例如用邏輯門） 。
  9. An embedded merging scheme for h. 264 avc motion estimation. in international conference on image processing, barcelona, spain, september 14 - 17, 2003, 1 : 909 - 912

    本文中的硬體電路主頻可以達到150兆赫茲，電路面積大約為212k邏輯門，能較好的完成可變塊大小的運動估計。
  10. Sorting algorithm can solve logic gate circuit for more fanout, more loop nestification and feedback alternately. we sort these nodes according to their joint relationship by the sort algorithm that can determine the priority order of digital circuit simulation and give the feedback chain

    排序演算法可以解決具有多扇出、多迴路嵌套及交叉反饋的邏輯門電路，按照其連接關系進行排序，並給出其中的最大反饋鏈。
  11. In order to enhance the applying efficiency of cl, the cause of premature convergence in binary - coded genetic algorithms ( gas ) is analyzed in this dissertation. the drawback of conventional mutation operator in preventing premature convergence is subsequently pointed out. whereafter, a genetic algorithm, which can be implemented via general logic gate circuit, is proposed

    為了提高計算智能的應用效率，本文分析了二進制遺傳演算法中早熟收斂的成因，指出了傳統的變異運算元在防止早熟收斂方面的不足，提出了一種能有效預防早熟現象的二元變異運算元，並在此基礎上提出了一種便於用常規邏輯門電路實現的遺傳演算法。
  12. With the rapid development of semiconductor, digital integrated circuit ( p, memory, standard logic gates, etc. ) and advance computer technology, the various measuring instruments ( virtual instruments ) with the powerful function of pc are produced in different industrial and scientific research fields. as we all known, the traditional instruments are usually built with discrete components and small scale ics, the disadvantages are obvious in system design, debugging and maintenance

    隨著半導體技術與數字集成電路（微處理器、存貯器以及標準邏輯門電路等）技術的迅速發展，特別是隨著計算機技術的發展，在工業生產和科學技術研究的各行各業中，人們利用pc機的強大處理功能代替傳統儀器的某些部件，開發出各種測量儀器（虛擬儀器） ，傳統儀器的數字邏輯部分多是採用分立集成電路（ ic ）組成，分立ic愈多，給系統的電路設計、調試及維護帶來諸多不便。
  13. Through analyzing the present chengdu electronic government network with the economical and practical thought, the paper propose a solution that selects domestic nc ( network computer ), domestic servers, and domestic linux os to build up a economical and adequate foundation information platform ; that uses open source java tools to develop essential and effective electronic government cooperation office software corresponding with our national conditions, addressing the demand of daily archives transfer, information communication and conference management ; that develops the data exchange engine based on xml and mail to apply safe data exchange between the office software in the electronic government network and the government portal in the internet, according to the logic separation of the electronic government network and internet

    本論文本著經濟實用的思想，利用成都市現有的電子政務網路進行合理劃分、設計，合理選型國產nc網路計算機（ networkcomputer ） 、國產linux操作系統來搭建經濟、夠用的基礎信息平臺：利用開源的java工具開發適合中國國情簡潔、有效的電子政務協同辦公軟體，可滿足政府日常公文流轉、信息溝通、會議管理等需求：根據電子政務外網與公網邏輯隔離的特點，開發基於xml和郵件的數據交換引擎實現電子政務外網中辦公軟體和公眾網中政府門戶網站的安全數據交換。
  14. A gate that performs the boolean operation of implication

    執行「蘊含」布爾操作的一種（邏輯）門電路。
  15. An electrical gate or mechanical device which implements the logical or operator. an output signal occurs whenever there are one or more inputs on a multichannel input. an or gate performs the function of the logical " inclusive or operation "

    一種實現邏輯「或」演算法的門電路或機械器件。當在其多通道輸入端有一個或多個輸入時就產生一個輸出信號。 「或」門實現邏輯「或操作」的功能。同orelement 。
  16. Teleportation of an unknown quantum state includes three processes, preparing entangled epr states, performing joint bell state measurements on the particle that will be teleported and one particle of the epr state, and then performing a unitary transformation on the second particle of the epr state. a scheme for teleporting an arbitrary three - particle state is proposed

    從基本的量子邏輯門討論出發，對單粒子、二粒子摘要激光駐波場中原子的動力學行為和量子態的隱形傳送任意量子態的隱形傳送過程建立了量子邏輯電路，為量子態隱形傳送過程的實現提供理論依據。
  17. In this paper an fault simulator for iddt testing is presented, which can detect concurrently the multi - faults. due to the subtle error among equipment manufacturing, the gate delays of circuits are not the same but range within limits. which induces the uncertainty of the waveform transforming time

    本文從故障激活的條件入手，利用五值邏輯，對瞬態電流測試中的延時變化進行波形分析和波形計算，採用並發模擬演算法，編程實現了一個iddt測試的故障模擬器。實際電路中由於製造工藝的限制，邏輯門的延時並不相同，而是在一定范圍內變化，引起波形變化的時間不確定。
  18. Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired

    在超導rsfq數字電路模型的理論分析基礎上，論文中採用wrspice對超導rsfq數字電路進行時域模擬，得到了超導jtl傳輸線，緩沖器， rs觸發器， t觸發器，或門等基本邏輯單元電路以及電路參數。
  19. It details the ic design process and vlsi circuits, including gate arrays, programmable logic devices and arrays, parasitic capacitance, and transmission line delays

    它詳細規定了集成電路設計過程和超大規模集成電路電路，包括門陣列，可編程邏輯器件和陣列，寄生電容，及輸電線路的延誤。
  20. A distinguishable faults test generation method for digital circuits is presented. the features of basic gate circuits and neural networks are used to establish the test model, and to generate the test patterns for given faults. the fault model and constrained circuit are studied. some strategies, e. g, the reduction of the size of neural network, are proposed in order to accelerate test generation process. the experimental results demonstrate that the algorithm proposed in the paper is effective

    研究一種基於人工神經網路的能區分故障的數字電路測試生成方法，該方法利用電路基本邏輯門的特性和神經網路模型的特點，首先建立測試生成的神經網路模型，然後通過求解網路能量函數的最小值點獲得給定類型故障的測試矢量，其研究結果在可區分故障的測試生成方面提供了一種可能的新途徑
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