配置寄存器 的英文怎麼說

中文拼音 [pèizhìjìcúnqì]
配置寄存器 英文
configuration register
  • 配 : Ⅰ動詞1 （兩性結合） join in marriage 2 （使動物交配） mate （animals） 3 （按適當的標準或比例加以...
  • 置 : 動詞1. （擱; 放） place; put; lay 2. （設立; 布置） set up; establish; arrange; fix up 3. （購置） buy; purchase
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 配置 : dispose （troops, etc. ）; deploy; allocation; collocation; configuration; positioning; allotment
  1. Initialize memory, which includes enabling memory banks, initializing memory configuration registers, and so on

    初始化內存，包括啟用內存庫、初始化內存配置寄存器等
  2. Because no drive software is needed in using chip 21154, this paper don ’ t refer to the drive design. after configuring the register in initialization rightly, the work about design of add - in card are all done

    因為橋晶元不需要驅動軟體，因此不需要進行驅動程序的設計，只需要在初始化的時候對配置寄存器進行正確的配置即可，這些工作在最後一部分完成。
  3. Configuration control register

    配置控制寄存器
  4. Also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals

    搭建了一個驗證系統，通過單片機來配置初始化寄存器和控制寄存器的值來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。
  5. The goal of this thesis is to accomplish base - band channel coding / decoding, fh framing / de - framing and fh synchronization, and also to control the modulator and demodulator in the prototype system. all these functions are implemented with a tms320vc5409 dsp

    作為項目的一個重要組成部分，本文採用dsptms320vc5409實現了基帶處理部分的通道編解碼、跳頻意義的組拆幀和跳頻同步、並對調制解調晶元讀寫寄存器進行了配置。
  6. The bus is programable. at this rate the user can program the mcu firmware to configure the correlative registers before using the bus. the user can also change the bus channel in the gpmb when the data of different type is to be transfered. in conclusion, gpmb module provides the communication channel between usb2. 0 ip core and peripheral

    它提供32位可編程介面，用戶可以通過usb2 . 0ip核中的mcu固件對內部相關寄存器進行配置來使用這32位總線，並可以在內部的多總線通道中切換，以達成usb2 . 0ip核對外圍介面的控制及數據傳輸，進而完成設備通過usb2 . 0介面ip核與主機通信的功能。
  7. What is the default configuration register setting on most cisco routers

    思科路由器的配置寄存器的值一般是多少？
  8. Known well vxibus criterion, the structure of configure register and vxi address mapped theory. known well the structure and work theory of high speed synchro data acquisition device

    熟悉vxi寄存器基器件的配置寄存器結構， vxi地址空間映射原理；熟悉高速同步採集卡的總體結構和工作原理。
  9. The control logic is completed by fpga. the system control software provides several control functions of pci and dsp, such as adjusting pci bus configure registers, setting work mode, downloading dsp programs and data, reading processing results from dsp and saving data

    系統控制軟體提供了pci和dsp的控制功能：修改pci總線的配置寄存器、設置工作方式、向各個dsp下載用戶程序與數據、從dsp中讀取處理結果、數據存檔等操作。
  10. Within this scope, users can get almost any frequency clock by configuring the register, as the tune - process is nearly continual ( in fact there are many discrete frequency points ). the main circuit of the clock generator is a cppll ( charge pump pll ) designed in a method

    該時鐘發生器可以向系統提供頻率范圍是93 . 75k - 180mhz的時鐘信號，用戶可以通過配置寄存器的方法使時鐘發生器輸出自己需要的頻率，而且這一調頻過程幾乎是連續的（實際上是眾多離散點構成的線性近似） 。
  11. Optimizing with profile data results in better register allocation. basic block optimization

    寄存器分配用配置文件數據進行優化，可以實現更好的寄存器分配。
  12. Making use of the powerful capabilities of the pci chip, high - speed data of the dsp platform are transferred both ways at dma mode, and low speed data such as initialization and configuration information are transferred at direct slave mode. this paper shows in detail the workings of pci9054, the configuration of its control register, and the writing of platform driver with api functions provided by the manufacturer

    利用pci介面晶元的強大功能，本文提出了採用dma模式雙向傳輸dsp平臺的高速數據，採用從模式傳輸初始化信息及配置信息等低速數據，並詳細介紹了pci9054的工作方式，控制寄存器的配置以及調用廠商提供的api函數編寫平臺驅動程序。
  13. In the first part, this paper discusses the key problems in designing architecture of each component, which include why we choose partitioned regiater files, use 2 - way connected data cache with write - back strategy and add scratch - pad sram to original momory system, and how to identify their parameters. following that, a memory configuration based on the discussion above is presented

    本文首先介紹了dpc各個存儲器的設計和實現，詳細討論了寄存器文件分體結構的選擇並提出了寄存器文件參數配置的四條規律，介紹了數據cache容量及策略的權衡與選擇，闡述了scratch - padsram與cache並存的優勢。
  14. 3. realize the interface between pci9054 and the pci bus, including the bus arbitration, read and write of the registers, the configuration of the eeprom, the dma transfer, interrupt response and so on

    3 .實現pci9054與計算機pci總線的介面，包括總線仲裁，寄存器讀寫操作， eeprom的配置和下載， dma傳輸，中斷響應等功能。
  15. The configure file is downloaded into the fpga chip according to the fpga design fl ow. also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals

    使用xillinx的fpgaxc2550pq208 ，經過fpga的實現流程，把配置文件配置到xczs5opqzos ，搭建了一個驗證系統，通過單片機來對各控制寄存器寫入控制字來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。
  16. The architecture - specific part of the kernel executes first and sets up hardware registers, configures the memory map, performs architecture - specific initialization, and then transfers control to the architecture - independent part of the kernel

    內核中特定於體系結構的部分首先執行，設置硬體寄存器、配置內存映射、執行特定於體系結構的初始化，然後將控制轉給內核中與體系結構無關的部分。
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