鎖存 的英文怎麼說

中文拼音 [suǒcún]
鎖存 英文
circuit, latch
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  1. The channel counter and decoder provide the channel select information to the data latch and transmit logic circuits.

    通道計數器和解碼器向數據鎖存和傳送邏輯電路提供通道選擇信息。
  2. Two other effects are transient phenomenon called single event upset ( seu ) and single event latchup ( sel ). in this paper, some means to harden the devices against these phenomena are used. guard banding around nmos and pmos transistors greatly reduces the susceptibility of cmos circuits to lachup

    在本文設計中，採用雙環保護結構，大大的降低了cmos集成電路對單粒子閂鎖效應的敏感性；對nmos管採用環型柵結構代替傳統的雙邊器件結構，消除了輻射感生邊緣寄生晶體管漏電效應；採用附加晶體管的冗餘鎖存結構，減輕了單粒子翻轉效應的影響。
  3. The dac consists of analog circuit blocks and digital circuit blocks, so it is a mixed signal circuit. because the digital part is simple comparatively, we use the same method as analog part to design it

    採用模塊化的設計方式實現數據快速轉換，主要包括電流源矩陣模塊、鎖存模塊、譯碼模塊、帶隙基準電壓源模塊及電流開關網路等電路模塊。
  4. In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework

    另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。
  5. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  6. After that, the hardware circuit, especially some of the key parts, is investigated in detail. the following processes are also investigated in detail : empoldering the four fold - frequency subdivision 、 direction - judgment 、 counting and flip - latch of the data with vhdl ( very high speed integrated circuit hardware description language ) ; empoldering the serial interface and the data collection software in pc with borland c + + builder

    接下來詳細介紹了使用vhdl語言開發fpga晶元的細分、辨向、計數、鎖存以及串列傳輸處理等全部功能;用borlandc + + builder開發了pc機上的串列介面、數據採集軟體;設計並製作了fpga晶元及其外圍電路的電路板。
  7. Provides a secure connection between the hard drive and the cable connector via a locking latch mechanism. ideal for

    -透過鎖定鎖存器裝置，為硬碟機和電纜連接器之間提供安全的連接。
  8. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。
  9. The four fold - frequency subdivision 、 direction - judgment 、 counting and flip - latch of the data which come from the six encorders are totally transacted in the fpga chip. the final data are sent to the pc through the serial interface of the fpga

    坐標測量儀的六個編碼器所傳出的數據完全在fpga晶元中進行細分、辨向、計數以及鎖存傳輸處理，最後所得的數據以串列通訊的方式傳送到pc機。
  10. Individuals who believe that their intellectual property rights have been infringed either on the internet or through online services provided by ctm may contact ctm, directly or through their authorized agents, and request that the infringing material be removed or access to it blocked

    如果任何人士認為其知識產權在澳門電訊的網際網路服務或聯線作業服務中受到侵犯，可直接或透過授權代理人與澳門電訊聯絡，要求移除或封鎖存取侵犯知識產權的資料。
  11. As the atom wiki states, the project creates " specifications for syndicating, archiving and editing episodic web sites. " i think that the defining characteristic of the domain atom addresses is not just web sites that are naturally broken into episodes, but also web sites that have a conversational nature through their interchange with other sites ; the episodes are often fueled by cross - reference to similar entries on other sites, and atom intends to be the glue for this interchange

    如atom wiki所宣稱的那樣，該項目要建立「連鎖、存檔和編輯情節式站點的規范」 。我認為， atom處理領域的定義特徵不僅僅是自然分解成情節的web站點，還包括那些與其他站點交互中具有會話性質的web站點。情節往往帶有對其他站點上類似實體的交叉索引， atom就是為了把這類交換粘結在一起。
  12. The analog input signal is latched on the rising edge of clk

    模擬輸入信號在clk的上升沿被鎖存。
  13. Controlling system is composed of drive circuit, locking memory, shift register. temperature compensating circuit and drive power circuit are also needed

    控制系統是由驅動電路、鎖存器、移位寄存器等組成，此外還需要溫度補償電路和驅動電源電路，本文對控制系統進行了詳細的論述。
  14. Desks, chairs, lockers ( 40. 5 cm in length and width, and 155 cm in height in principle ), lockable file cabinet for storage of documents, air conditioner and direct - dialing telephones shall be furnished in the office

    辦公室應備桌椅、衣櫃（其尺寸以長、寬、高各為四、四五及一五五公分為原則）及能加鎖存放報表、文件之檔案櫃、空調設施及直撥電話。
  15. Port c is also used in mode 1 operation - not for data, but for control or handshaking signals that help operate either or both port a and port b as strobed input ports

    我覺得翻成「模式1選通輸入」比較好一點，而010698 ， 010700翻成了「模式一觸動式輸入」 ， 010750 「模式1鎖存輸入」 ， 010820翻成了「模式1濾波輸入」 。
  16. 3 scan controlling card the same kind of circuitry board which compatible outdoor one in fourth scan, one in second scan and the whole static state work way 4

    3控制卡：採用全鎖存靜態恆流工作方式，在提高亮度的同時降低系統發熱，在扼制系統電流波動同時有效地控制色溫。
  17. The time division circuit and latch counter are integrated in one chip of programmable logic device, which makes the size greatly decreased

    同時採用cpld晶元實現了時間分割電路和計數鎖存電路，有效地減小了電路體積。
  18. High ? speed synchronized latch circuit and special clock driver are used, which adapt to the requirement of quick data - transformation with high accuracy and low power

    採用高速同步鎖存電路和特殊結構的時鐘驅動電路，在保證精度和功耗設計要求上，實現數據快速轉換。
  19. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  20. Once digitized at baseband, they can be stored in memory and recalled to generate the desired waveform

    設計中大量的使用了ecl邏輯的晶元，諸如鎖存器，移位寄存器等等。
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