鎖模塊 的英文怎麼說

中文拼音 [suǒmókuāi]
鎖模塊 英文
lock plate
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 塊 : 名詞（古時佩帶的玉器） penannular jade ring （worn as an ornament in ancient china）
  • 模塊 : camac module,camac
  1. Contrapose to the instability of the third - order charge - pump pll system, the loop optimization method is employed in system level design to decide the bandwidth and phase margin, therefore the loop bandwidth locates at the maximum phase margin to guarantee the stability of the system. according to tsmc 0. 35 m sige bicmos model, the sub - circuits in the designed pll and the whole system are simulated and verified by the cadence spectre

    5 .根據tsmc0 . 35 msigebicmos工藝模型，利用cadencespectre模擬軟體對所設計的電荷泵鎖相環路中各個模塊及整個系統進行了模擬模擬，模擬結果顯示，在1 . 5v電源電壓下，頻率為200mhz的參考輸入信號，輸出中心頻率為800mhz ，分頻電路採用4分頻，環路帶寬為10mhz ，捕獲時間大約為0 . 92 s ，功耗大約為15mw ，達到了設計指標。
  2. Development of hybrid integrated circuit of high linearphase - locked frequency discriminator

    混合集成電路高線性鎖相鑒頻模塊的研製
  3. This paper presents a method that chopping wave is done by switch devices which consist of three - level resistance regulating module and intelligence power module ipm, and which realizes constant - current discharge of storage battery. to achieve the intelligence control of the drive protection and the discharge process of ipm, the paper designs circuit formed by igbt threshold drive pulse pwm signals. ipm fault - blocking protection circuit and microcomputer 80c196. the devices can accurately control the 0 ~ 150a discharge current and the discharge time of the storage battery and calculate the releasing power

    實現蓄電池恆流放電過程智能控制是蓄電池放電裝置發展的必然趨，本文提出了一種通過三極電阻調節模塊和由智能功率模塊ipm為開關器件進行斬波從而實現蓄電池恆流放電的方法。為達到對ipm的驅動保護和放電過程的智能控制，文中設計了igbt門極驅動脈沖pwm信號形成電路和ipm故障封鎖保護電路及由單片機80c196為核心的微機控制器。本裝置能夠對蓄電池進行0 150a放電電流及放電時間的精確控制及釋放容量的計算。
  4. In allusion to the working characteristics and technical difficulties of 155mb / s burst mode receiver, we have put forward to the quick synchronization of inpouring phase locked loops ( pll ). for receiving burst signal, we introduce the scheme of dc coupling and dynamic threshold decision

    針對155mb s突發式收發模塊的工作特點和技術難點，我們提出了注入鎖相環法的快速同步技術；對于突發式信號的接收，我們採用了直流耦合和動態閾值判決的技術方案。
  5. The dac consists of analog circuit blocks and digital circuit blocks, so it is a mixed signal circuit. because the digital part is simple comparatively, we use the same method as analog part to design it

    採用模塊化的設計方式實現數據快速轉換，主要包括電流源矩陣模塊、鎖存模塊、譯碼模塊、帶隙基準電壓源模塊及電流開關網路等電路模塊。
  6. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  7. 3 ) the content of generator module design includes the design factor, design outline, software design and experimentation. the generator module must complete the analog signals calculating, and make an order for shutting off connected generators in the condition of generators settings, concatenated logics and switch signal input, then communicate with the decision module

    3 ）發電機模塊的設計內容包括設計考慮因素、設計要點、軟體設計以及實驗驗證等，模塊必須完成對接入的發電機機組模擬量的計算；在機組設置、連鎖邏輯和開入信息等條件下對接入的發電機機組排出一個切機順序；完成模塊間通信。
  8. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  9. This thesis describes the properties of millimeter wave, and development of the millimeter wave sources nowadays, and introduces the solid - state devices impatt diodes, and analyses the technology of the injection locked. then this thesis gives out how to design the pa module in detail. and practical circuit is given out with the test result and analyses

    本文首先綜述了毫米波特點，毫米波源的發展現狀，介紹了w波段impatt器件的基本工作原理，分析毫米波波導電路中的注入鎖定技術，給出實現連續波或脈沖功率放大的w波段信號源的功放模塊的技術方案、測試結果和綜合分析。
  10. To that end, the threading module provides a number of synchronization primitives including locks, events, condition variables, and semaphores

    最終，線程模塊提供了幾個基本的同步方式如鎖、事件，條件變量和旗語。
  11. Pll frequency synthesizer is increasingly used in microprocessor systems and communication. with the development of integrated circuits and the emergence of soc ( system on a chip ) technology, it has been a fundamental and very important module in analog and mixed - signal integrated circuits

    鎖相環頻率合成器現在日益廣泛地應用於通訊、微處理器系統中，並且隨著集成電路的發展以及soc技術的出現，其已經成為超大規模集成電路中不可或缺的模塊。
  12. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。
  13. The system is composed of parallel microprocessor interface, spwm generator, deadtime compensation module and pulse blocking module. the pwm pulse signal is automatically generated as soon as the control variables ( s, x ) input from microprocessor

    該系統由并行微處理器介面、 spwm脈沖發生模塊、死區補償模塊和脈沖封鎖模塊組成，可以按照微處理器給定的控制變量、自行產生觸發脈沖。
  14. Critical circuits in developing this board, such as tht modulation circuit, demodulation circuit, pll and filter, were analyzed in detail. parameters adopted in these circuits were also calculated. based on all that mentioned above, a rf board was implemented and related tests and experiments were successfully done as well

    本文主要對cdpd移動終端數據機的硬體開發中的關鍵部分?高頻部分電路進行了研究，論文在cdpdv1 . 1規范的基礎上，提出了射頻部分電路的實現方案，選擇了合適的核心晶元，並對電路中的調制解調電路、鎖相環、濾波器等關鍵模塊進行了較為詳細的分析，對電路中的有關參數進行了計算。
  15. The paper compares some algorithms on rs decoding, makes improvements based on the me algorithm, removes the modifying step in decoding truncate rs code, corrects unsuitable statements in the related papers, and parameterizes the rs decoding module, reducing its area by 20 %. the paper overcomes the signal integration problem in multi - clock design, greatly lowers the phase jitter without area increase, introduces pll to adjust rate for the first time, and parameterizes the module

    本文比較了實現rs解碼的幾種演算法，並在me演算法基礎上進行改進，創造性的去掉了縮短碼解碼中的校正環節，糾正了有關論文中的不當論述，並將rs解碼模塊進行了參數化設計，同時也將rs解碼的規模縮小了20 ；克服了多時鐘設計中的信號完整性難題，在沒有增加模塊面積的條件下，大幅降低數據的相位摘要抖動，首次引入鎖相環來調整速率。
  16. The principle and structure of pll ( phase - locked loop ), including fll and loop filter, are analyzed and described. the module of carrier synchronization in the all - digit ds - qpsk receiver was carried out in the fpga chip. the problem about the estimation and track of the correlative carrier frequency under high dynamic circumstances was resolved very well

    針對某遙測遙控全數字接收機的研製，對相干載波同步中的鎖相環、鎖頻環、 dpll 、本地nco等進行了詳細的分析和優化設計，在fpga上實現了高動態全數字ds - qpsk接收機中的載波同步模塊，解決了大范圍和動態多普勒頻移下接收機的相干載波提取與跟蹤問題。
  17. In the thesis, some of the most important functional modules of the smart power control ics are researched and designed, including voltage reference, voltage regulator, under voltage lockout, oscillator and zero - voltage comparator. their topologies, schematics and layouts are introduced and developed

    本畢業設計研究和提出了構成智能電源控制晶元的主要功能模塊，完成了其中若干模塊ip核的電路與版圖設計? ?包括基準電壓源，電壓調節器，欠壓鎖定比較器，振蕩器，電壓過零比較器等。
  18. Ci - xx : mechanical interlock cne - xx : coil drive unit for ac or dc operated

    機械連鎖模塊，可防止正逆轉誤動作產生的短路。
  19. The “ commtor ” module is the foundation of the entire dplib. all the other modules rely on this module

    通信子模塊是整個分散式并行函數庫的基礎，其他模塊（除了流水鎖模塊）的實現都依賴于該模塊。
  20. According to this thought, this thesis decomposes the consistency question into two aspects : the transaction result consistency and the transaction sequence consistency. we designed two modules to solve these problems : the “ synctor ” module and the “ pipeline lock ” module. the “ synctor ” module is able to call the same function at the remote nodes

    本論文按照這個思想，將一致性問題分解成事務結果一致性和事務執行順序一致性兩個方面，並分別設計出同步子模塊和流水鎖模塊來解決這兩個方面的問題。
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