鎖相電路 的英文怎麼說

中文拼音 [suǒxiāngdiànlù]
鎖相電路 英文
phase lock circuitry
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  • 相 : 相Ⅰ名詞1 （相貌; 外貌） looks; appearance 2 （坐、立等的姿態） bearing; posture 3 [物理學] （相位...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. Contrapose to the instability of the third - order charge - pump pll system, the loop optimization method is employed in system level design to decide the bandwidth and phase margin, therefore the loop bandwidth locates at the maximum phase margin to guarantee the stability of the system. according to tsmc 0. 35 m sige bicmos model, the sub - circuits in the designed pll and the whole system are simulated and verified by the cadence spectre

    5 .根據tsmc0 . 35 msigebicmos工藝模型，利用cadencespectre模擬軟體對所設計的電荷泵鎖相環路中各個模塊及整個系統進行了模擬模擬，模擬結果顯示，在1 . 5v電源電壓下，頻率為200mhz的參考輸入信號，輸出中心頻率為800mhz ，分頻電路採用4分頻，環路帶寬為10mhz ，捕獲時間大約為0 . 92 s ，功耗大約為15mw ，達到了設計指標。
  2. Development of hybrid integrated circuit of high linearphase - locked frequency discriminator

    混合集成電路高線性鎖相鑒頻模塊的研製
  3. In the next place, by studying the change of the resonant frequency of the whole system, this paper designs the circuit to track the resonant frequency of the system by cd4046 mainly. at the same time, in order to improve the efficiency and get better dynamic capability of the converter, we choose pll and fuzzy control after comparing the pll circuit, fuzzy circuit and pll ? fuzzy control circuit. in the end, this paper brings forward the control blue print to realize the drive control circuit of the high frequency converter, using the dsp chip as the key part to realize four routes of pwm drive pulses with dead band of the control system

    其次，通過對整個系統諧振頻率變化的分析和研究，設計了以鎖相環cd4046為核心的鎖相環控制電路，同時，在綜合比較鎖相環控制、模糊控制以及模糊控制和鎖相環復合控制三種控制演算法的基礎上，進行了系統模擬，得出採用復合控制可使跟蹤電路既具有鎖相環路較好的穩態性能，又擁有模糊控制較好的動態性能，系統魯棒性能好，同時也提高了逆變器的效率。
  4. Choosing y type reflection fiber optic detector, this thesis create a tiny displacement - detecting sensor that is made up of led ( light emitting diode ), fiber optic detector, electric eye, lock - in amplifier, display and other electro circuits

    本論文採用y型反射式光纖探頭設計製作了一種微位移測量裝置，它主要由發光二極體、光纖探頭、 、鎖相放大器、顯示器及相關電路組成。
  5. Monitor apparatus can measure valid value of three phase voltage and current, power factor, three phase disequilibrium, instant flecker of short time and harmonic without twenty, degree and harmonic distortion total. the paper are laid on the following. ( 1 ) master plan and function of circuit, ( 2 ) hardware design including circuit and principle of a / d conversion, phase lock, liquid crystal display and keystroke and so on, ( 3 ) design of system software including digital filtering, fft, a / d conversion and monitor interface of pc, ( 4 ) system test

    監測儀能夠完成包括三相電壓、三相電流的有效值、功率因數、三相不平衡、電壓短期閃變、以及20次內的諧波、諧波相位、諧波失真總量等的測量。論文重點介紹了以下幾部分： （ 1 ）電路的總體設計和功能； （ 2 ）硬體設計，包括a d轉換、鎖相環、液晶顯示和按鍵輸入等原理和電路。 （ 3 ）系統軟體設計，包括a d轉換、 fft 、數字濾波等程序的原理和演算法以及上位機監控界面的設計； （ 4 ）系統測試。
  6. Design of hardware consists of three pll loops, micro wave sample mixer, fractional - n frequency divider

    硬體電路包括三個鎖相環，取樣混頻器，分數分頻器的設計等。
  7. In this thesis, firstly, we put forward a new algorithm of the synchronization of carrier reference phase, that is to use the curve synthesizing with the general digital carrier phase looper to have an estimation on carrier frequency within 10 ms so as to meet the need of meteor burst communication. we have done some simulations to get the performance of carrier frequency estimation using two modulation modes ( 16qam and 4 - qpsk ), and had some test on the carrier phase looper in conditions when using different baud rate transmission and when the baud tuning have windage

    我們對兩種正交調制方式（ 16qam和4 - qpsk ）進行了模擬工作並給出了模擬結果，同時討論了碼元同步定時誤差對鎖相環路工作的影響並根據流星通信中使用變速率傳輸時鎖相環路的載波同步性能進行了測試；然後在基於軟體無線電思想的數字處理平臺（該數字處理平臺實現了中頻數字化）上用dsp軟體完成了載波的相位跟蹤。
  8. The designs of the pfd, digital filter ocxo and fractional - n counter in the frequency synthesizer unit are discussed, based on the pll theory. in order to improve the precision of pll, some design methods of pfd are given, and its feasibility is validated by the fpga hardware implement

    2 .在鎖相理論指導下，第三章討論了頻率合成器設計中的鑒頻鑒相器、數字濾波器、恆溫壓控振蕩器和分頻電路設計。為了進一步提高頻率合成的精度，文中給出了提高鑒頻鑒相器性能的一些設計思想，結合fpga的硬體設計驗證了其可行性。
  9. Thus the principle to deal with the four basic waveforms is put forward and a new phase - demodulation circuit is designed. experiments for the two circuits on same gyros are made and they indicate clearly that the mdrlg ' s null - shift problem consists in the faultiness of the old phase - demodulation circuit

    在此基礎上，提出了處理計數信號過鎖區波形的基本原則，進而設計了新的鑒相電路，並在同一陀螺上對兩鑒相電路進行了對比實驗。
  10. Firstly, computer model of mdrlg is set up for simulation purpose. by simulation about the two output signals of mdrlg, four basic waveforms between the two signals in lock - in area are found out and the fact is discovered that the old phase - demodulation circuit introduces errors when it is used for demodulating two of the four basic waveforms

    本文首先建立了機抖陀螺的計算機模擬模型，利用該模型對陀螺兩路計數信號及原有鑒相電路進行了模擬，發現兩路計數信號過鎖區時存在四種基本波形，且原有鑒相電路對其中兩種波形產生鑒相誤差。
  11. The basic operation principle of phase - locked frequency synthesizer and the type of circuits are expatiated systematicly in this paper. the principle of operation on sampling phase detector and some characteristics including the linear tracking and phase noise in phase loop circuits are analyzed deeply. the research is emphased on the theory and design method of circuits in the sampling phase - locked frequency synthesizer. then, the expansion capturing circuit is analyzed and designed for better performance of capturing loop circuits. at last, the loop filter is also analyzed and contrived taking account of effection of additional phase shift by the sampling - holder. the general research on the theory and technology of sampling phase lock in the paper will make a basement for the development of new product

    本文系統的闡述了鎖相頻率合成器的基本工作原理及電路類型；較深入地分析了取樣鑒相工作原理及電路、鎖相環路的線性跟蹤特性和相位噪聲特性；重點對取樣鎖相頻率合成器電路理論和設計方法進行了研究；為了改善環路的捕獲性能，對擴捕電路進行了分析和設計，並用wewb32軟體對電路進行了模擬；考慮到取樣保持器的附加相移影響，對環路濾波器進行了分析和設計。
  12. And the new circuit structure for improving the locking range, that is, injection - locked phase - locked loop circuit ( ilpll ) is introduced into the millimeter wave circuit

    在此基礎上，結合注入鎖定和環路鎖相原理，在毫米波頻率源中引入了一種新型的展寬帶寬的電路結構環路注入鎖定鎖相電路（ ilpll ） 。
  13. In this paper, a pll frequency synthesizer working in l band is researched. at fist, we review the basic of phase lock loop and it ' s constituent part. after that the basic conception and design method of pll frequency synthesizer was introduced, especially introduced the charge pump pll frequency synthesizer in detail

    本文是採用鎖相原理設計的l波段頻率合成器，首先對鎖相環路的工作原理和基本組成部分進行了簡單的介紹，然後介紹了鎖相頻率合成器的原理和設計方法，主要介紹了目前小型頻率合成器產品中使用最廣泛的由電荷泵數字鑒頻鑒相器和無源環路濾波器構成的頻率合成器。
  14. Application of dsp in the optic - electric measuring system

    倍頻鎖相電路在非標準圖像採集系統中的應用
  15. Dds is used to achieve fine resolution, while injection phase lock circuit is used to realize low phase noise high performance input reference frequency

    Dds用於實現小步進，而注入鎖相電路則用來產生低相噪的高性能參考源。
  16. Then according to the emphasis of the design, went deeply into the theory of pll frequency synthesizers widely used, described pll ’ s working principle, structure and several types in detail, and made research and analysis of pll frequency synthesizers ’ phase noise, including the effect of the active loop filter on the phase noise, and give some methods to make improvement as well, such as changing loop filter form, reducing divide number, and increase phase detector frequency, etc. then paper introduced the principle character and phase noise analysis of direct digital frequency synthesizer ( dds ) and injection phase lock circuit, which are also important circuits in the design

    論文首先對幾十年頻率合成器的發展進行概述，而後針對本次設計的重點，對應用較為廣泛的鎖相頻率合成理論進行了深入的探討，詳細介紹了鎖相環的工作原理、組成結構和鎖相類型，並對鎖相頻率合成器的相噪特性進行了研究分析，包括有源環路濾波器對于相噪的影響，提出了改善相位噪聲的幾點措施:改善環路形式、降低分頻數、增大鑒相頻率等。接著介紹了直接數字頻率合成器（ dds ）和注入鎖相電路的原理特點以及相噪分析，它們也是本次設計的重要電路。
  17. Moreover, its interior pll circuit substitutes traditional pll. as a result, the presented design not only overcomes some shortcoming of traditional circuit such as tracking speed and accuracy, but also gets rid of response lag time and multi - phase noise. the system design is also important to improve our country ' s fault diagnosis standard

    而該系統內部鎖相電路代替了傳統方法中的pll ，因此，提出此系統設計不僅能夠克服基於傳統鎖相環電路的等轉角采樣方法跟蹤精度低、速度慢和使用不便等特點，還能克服電路中的由於不可避免的響應延遲時間所導致的不適合快速的列車運行及過多的相位噪聲問題，對于推動我國鐵路故障在線診斷技術的應用普及具有重要意義。
  18. Through the combination of inverter circuit and pll circuit, the process of frequency - tracking is described, and the experimental waves can be reflected perfectly. this provides some experience for the designing and debugging of electrical source

    並將鎖相環路與主電路結合起來，觀察到頻率跟蹤的過程，很好的反映了實際波形，為今後該類電源裝置的設計調試提供了良好的前期準備。
  19. We design the digital phase - locked loop applying the method designing digital circuitry from the top down. we design the circuitry by the vhdl in the maxpulsii software environment. we validate the circuitry function in the emulator

    採用自頂向下的數字電路設計方法設計全數字鎖相環路，在maxplusii設計環境下採用vhdl語言、 ahdl語言等設計實現數字鎖相環，並通過計算機模擬證實其正確性。
  20. On basic of researching the principle of phase locked loop, this article analyzes the output signal whose noise characteristics depend on the each part of pll, and designs a scheme to realize the frequency synthesizers using the high performance chips with integrated prescalers and phase detectors. the visualized circuit structure is given in this paper

    本文在研究鎖相環路基本原理的基礎上，分析了鎖相式頻率合成器電路中各部件對環路輸出信號噪聲性能的影響，設計了以一個高性能的集成鎖相環頻率合成器晶元為基礎實現頻率合成的方案，並給出了具體的電路形式。
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