鐘觸發器 的英文怎麼說

中文拼音 [zhōngchùfāqì]
鐘觸發器 英文
master slave fliflop
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 觸 : Ⅰ動詞1 （接觸） touch; contact 2 （碰; 撞） strike; hit 3 （觸動） touch 4 （感動） move sb ; sti...
  • 發 : 名詞（頭發） hair
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 觸發 : detonate by contact; touch off; trigger; strike
  1. In a synchronous counter all stages are triggered by a common clock.

    在同步計算器中，所有觸發器均由同一個時鐘觸發。
  2. The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse.

    每當計數器被時鐘脈沖觸發一次時，計數器輸出的二進制數便累減1。
  3. In addition, a novel heuristic approach which we called “ improved simulated annealing algorithm ” is proposed for bounding maximum and minimum leakage power. 2. a design method for low power clock network is proposed

    通過對高性能通用處理器中時序邏輯特點的詳細分析，提出採用帶門控使能的多比特觸發器設計方法來降低時鐘功耗。
  4. The developed apparatus can automatically measure evapotranspiration at setting up interval and memory the data through a 32 kilobyte data storage memory. measured data can be transmitted to personal computer by rs232 series communication interface. apparatus will be trigged at measurement time by a real time chip set in it

    該儀器通過實時時鐘晶元實現間隔採集動作的觸發及時間、日期的計數；利用液晶顯示器（ lcd ）進行顯示；使用它能在無人監管的工作環境下，定時進行蒸散測量並將測得數據自動保存到32k數據存儲器中；再通過rs232串列通訊介面將數據傳送到pc機進行進一步處理。
  5. The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse

    每當計數器被時鐘脈沖觸發一次時，計數器輸出的二進制數便累減1 。
  6. This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution

    主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。
  7. Furthermore, low power flip - flop design by reducing the short - circuit power which relates with clock overlapping is also mentioned in this paper

    此外，由於觸發器的短路功耗和控制觸發器的時鐘信號的交迭程度有關，因此文章還對通過合理規劃時鐘信號的交迭來達到減少觸發器短路功耗的低功耗觸發器結構進行了討論。
  8. The whole pwm circuit contains two subcircuit, the front - end is pwm module that make up of the counter that based on nine mosfet true - single - phase - clock d flip - flop ; the back - end is demodulated module, which is consist of a three order chebyshev low - pass filter used trans - conductor capacitor. all the subcircuits are simulated. at last, an approving simulated result of the whole circuit is given too

    在調制部分，利用九管單相時鐘d觸發器構成計數器，並由此組成了脈沖寬度調制電路，同時給出了在典型溫度下的模擬結果;在解調部分，介紹了低通濾波器從無源到有源的設計方法，設計了三階切比雪夫低通跨導電容濾波器，同樣給出了相應的模擬結果;最後，作為將脈沖寬度調制電路和濾波器作為整體電路，以脈沖調頻波為輸入進行了模擬，取得了令人滿意的結果。
  9. According to elaborate analysis of clock logic in general purpose processor, we apply multi - bit clock gated flip - flops design to reduce the power of registers and clock trees concurrently, so the power of the clock network in processors can be drastically reduced. 3. a low power issue queue architecture is proposed

    一方面利用帶門控使能的觸發器電路降低時鐘節點的平均翻轉，另一方面通過多比特觸發器的採用進一步降低了時鐘樹規模，從而在不增加asic物理設計復雜度的情況下大大降低了龍芯處理器的時鐘網路功耗; 3 .提出了亂序多發射隊列的低功耗結構。
  10. In the time - domain, based on the principle of random sampling of dso. two way ( " time amplifing in dual slope integral " and " time - voltage convert " ) are implemented to measure the time between the system triger and writing clock. thus random sampling interpolate can be done to measure repeated signal in high frequency with the a / d convert and controller which frequency are lower

    在時域，根據數字示波器隨機取樣原理，用兩種方法（雙斜率積分時間放大測量方法和時間? ?電壓轉換測量方法）測量數字示波器系統觸發和采樣寫時鐘間時間間隔，用低速a / d轉換器及控制器進行模?數轉換和控制，以此進行隨機取樣內插，從而實現了對高頻率重復信號的測量。
  11. According to the reserved scanning address sequence, channel range and trigger mode, it can sample data. the module can change sample time and sample length. the sample data can be disposed by the cpu on board and then be stored in 64k ram

    本模塊可根據預先設置的掃描地址序列、通道量程和觸發方式進行數據採集，采樣時鐘和采樣長度可以改變，測得數據經過板上cpu的實時處理后在64k的存儲器中緩存。
  12. According to the redundancy in digital circuits, we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits. to erase the redundant transition of the clock, the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design

    為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計並應用於時序電路設計中。
  13. In this paper, low power flip - flops designs by the reduction of the load of clock or the data path ; by the reduction of clock swing ; by the reduction of clock frequency and by the reduction of those idle transitions in cmos circuits with clock gating are discussed

    與此相對應的，在本論文中，分別對將少時鐘負載或數據通路的負載的觸發器設計；減小時鐘信號幅度的觸發器設計；降低時鐘頻率的雙邊沿觸發器設計以及應用門控技術來減少觸發器無效跳變設計的觸發器結構進行了討論。
  14. Dynamic power is dominant component of the average power dissipation in cmos circuits. and the value of dynamic power is determined by node capacitance, supply voltage, clock frequency and switching activity of cmos circuits. so most low power designs are achieved by reducing one or more those above parameters

    由於cmos電路的功耗與cmos電路的負載電容，電壓，時鐘頻率及開關活動性有關，因此在低功耗cmos觸發器設計過程中，許多低功耗設計技術都可以歸結到通過減小上面的參數來達到低功耗的目的。
  15. The content of fpga is downloadable via prom, jtag or the special port on chip by xilinx software. the module can delay input signals from 0ns to 1. 8us stepping by 25ns. it ' s precision is 25ns

    插件經過測試，能在0 71時鐘周期之間，以一個時鐘周期為步長實現對輸入信號的可編程延遲，延遲精度為25ns ，滿足觸發判選系統總觸發邏輯對齊來自各個探測器觸發子系統信號的要求。
  16. To avoid the idleness state and the corresponding power dissipation in sequential circuits, a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation

    為抑制時序電路中的冗餘現象，研究了時序電路的門控時鐘技術，並利用t型觸發器進行時序電路設計。
  17. The main contribution of the thesis is seen as follows : aiming at the fault with slow speed and high power dissipation of the conventional phase - frequency detector, a high speed and low power dissipation phase - frequency detector is designed by modifying the structure of the single phase lock dynamic d flip - flop and adding the delay cell in the feedback loop to eliminate the phase detector ’ s dead zone effectively

    論文的主要貢獻為以下幾個方面: 1 .針對傳統鑒頻鑒相器速度慢、功耗高的缺點，改進了單相時鐘動態d觸發器的結構，設計出了一種高速低功耗的鑒頻鑒相器，在反饋迴路上加入延遲單元，能有效的消除鑒相死區。
  18. Based on the construction of traditional flip - flop, we propose a novel edge - triggered flip - flip using one latch controlled by narrow pulse according to race - hazard of clock. then this principle is adopted in ternary circuit, a new ternary d type edge - triggered flip - fiop based on cmos transmission gate is proposed

    在二值單閂鎖結構邊沿觸發器的基礎上，把利用時鐘信號競爭冒險的思想應用於三值電路中，提出了基於cmos傳輸門的二值d型時鐘信號競爭型邊沿觸發器。
  19. In this clock system power, 90 % is consumed by the flip - flops themselves

    而其中觸發器所消耗的功耗有占時鐘網路功耗的90 。
  20. From function equations of different kinds of flip - flop integrated circuits, we discussed the methods of function change from final product jk of d flip - flop to other kind in use

    從各種時鐘觸發器的特性方程出發，討論了實際生產的集成時鐘觸發器jk型和d型向實用中可能使用的其他各類觸發器轉換的方法
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