閂鎖電路 的英文怎麼說

中文拼音 [shuānsuǒdiànlù]
閂鎖電路 英文
latch circuit
  • 閂 : Ⅰ名詞（門閂） bolt; latch Ⅱ動詞（用閂插上） fasten with a bolt or latch
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. Two other effects are transient phenomenon called single event upset ( seu ) and single event latchup ( sel ). in this paper, some means to harden the devices against these phenomena are used. guard banding around nmos and pmos transistors greatly reduces the susceptibility of cmos circuits to lachup

    在本文設計中，採用雙環保護結構，大大的降低了cmos集成電路對單粒子閂鎖效應的敏感性；對nmos管採用環型柵結構代替傳統的雙邊器件結構，消除了輻射感生邊緣寄生晶體管漏電效應；採用附加晶體管的冗餘鎖存結構，減輕了單粒子翻轉效應的影響。
  2. Research on cmos latchup

    電路中的閂鎖效應研究
  3. The n / n + and p / p + epitaxial structures, which become popular with the development of coms technology, because they can avoid the latch - up and a softerror of ulsi while they combined with the intrinsic gettering ( ig ) technique

    Coms工藝中普遍採用n / n ~ + 、 p / p ~ +的外延結構，這種以重摻雜矽片為襯底的外延結構與內吸雜工藝相結合，是解決集成電路中的閂鎖效應和粒子引起的軟失效的有效途徑。
  4. Soi hvic ( silicon on insulator high voltage integrated circuit ) is the mainstream and trend of the power integrated circuit ( pic ) due to the improved no latch - up, reduced leakage current, perfect irradiation hardness, and improved insulation

    Soi （ silicononinsulator ）高壓集成電路具有無閂鎖、漏電流小、抗輻射、隔離性能好等優點，已成為功率集成電路（ powerintegratedcircuit ）的重要發展方向。
  5. Recently, the n / n + and p / p + epitaxial structures have been applied in the study and production of microwave transistor and ultra - large - scale integrated circuits ( ulsi ), and the memorial maintain time of dynamic random access memory can be improved, latch - up effect and soft - error induced by a particles can be resolved through the combination of epitaxy and ig

    採用這種結構與ig工藝相結合，能夠大大地提高動態存儲器dram的記憶保持時間，是解決電路中閂鎖效應（ latch - up ）和粒子引起的軟失效（ soft - error ）的最佳途徑。
  6. Designs of redundant, radiation hardening and anti - lock of cmos integrate circuit were developed as the reliability steps of the on - board embedded computer system

    提出了利用一定冗餘備份的容錯設計技術、計算機抗輻加固技術和cmos集成電路抗閂鎖技術等提高星載嵌入式計算機系統可靠性的措施。
  7. Based on the construction of traditional flip - flop, we propose a novel edge - triggered flip - flip using one latch controlled by narrow pulse according to race - hazard of clock. then this principle is adopted in ternary circuit, a new ternary d type edge - triggered flip - fiop based on cmos transmission gate is proposed

    在二值單閂鎖結構邊沿觸發器的基礎上，把利用時鐘信號競爭冒險的思想應用於三值電路中，提出了基於cmos傳輸門的二值d型時鐘信號競爭型邊沿觸發器。
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