電路邏輯 的英文怎麼說

中文拼音 [diànlùluó]
電路邏輯 英文
circuit logic
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  • 邏輯 : logic
  1. This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite, and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite, a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward. then the research of software fault tolerant technique which is based on the operate system named rtems has been carried, the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward, at the same time the self - repair technique of software which has used the technique of system re - inject has been studied. finally the technique of components level fault - tolerant based on fpga has been studied, a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward, and the augmentative of circuit that project design realization need is little, this project can avoid any breakdown of any part logic circuit of the fpga

    本課題主要針對星載并行計算機體系結構及軟體結構的特點，從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基於星載多cpu并行計算機體系結構的系統級容錯模型研究，提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然後進行了基於rtems操作系統的軟體容錯技術研究，提出了任務級容錯調度演算法以及基於檢查點技術的系統級容錯恢復機制和策略，同時研究了利用系統重注入進行軟體在線自修復的容錯技術;最後研究了基於fpga的部件級容錯技術，提出了對容錯模塊這一星載并行計算機關鍵部件的兩級容錯方案，實現該方案所需增加的電路少，可避免板級晶元以及fpga晶元內部任何邏輯發生單點故障。
  2. The reasoning process called for by boolean algebra are implemented through switches, acting as electronics logic circuits

    布爾代數所需的推理過程是通過開關來實現的，這些開關起著邏輯電路的作用。
  3. The circuits driving the ccd and processing the video signal are implemented by means of cpld ( complex programmable logic device ) and hdl ( hardvvare description language ). the solution to solve the problem of multi - level logical competitive risks that occur in cpld circuits frequently was provided in details in the thesis

    Ccd的驅動電路和視頻信號處理電路採用cpld （可編程邏輯器件）和hdl （硬體描述語言）實現，文章對cpld電路中容易出現的多級邏輯冒險競爭情況作了專門的敘述和提出相應的解決方法。
  4. One way of overcoming this problem is to incorporate logic circuitry.

    解決這個問題的方法之一是引入邏輯電路。
  5. The method of connecting timing into 1ogic i s explained in waveform po1ynomia1 on the basis of waveform concept in boo1ean process theory. and an ana1ytica1 de1ay mode1 that is close to practice circuits is found

    並在布爾過程論中定義波形的基礎上，說明了邏輯與時序在波形多項式中的結合方法，建立了接近實際電路的解析延遲模型。
  6. Complementary constant current logic circuit

    互補恆流邏輯電路
  7. The parallel form of the input sequence is decoded by means of a logical decoding circuit.

    此并行形式序列通過邏輯解碼電路輸入。
  8. The channel counter and decoder provide the channel select information to the data latch and transmit logic circuits.

    通道計數器和解碼器向數據鎖存和傳送邏輯電路提供通道選擇信息。
  9. The thesis presents a expert system for identifies power quality disturbance signal, after compare the artificial neural network, nearest neighbors, fuzzy decision, and expert system. we bring forward the project flexible rule - based expert system, according to the characteristic inspection and measure system, and has a deep research on the problem of this system. this project for disturbance classifies has lower mistake ratio and facility maintenance

    採用專家系統的方法進行模式識別，在對神經網路、最近鄰法、模糊邏輯和專家系統及一些交叉方法等模式識別方法進行比較分析的基礎上，根據電能質量信號故障分析的特點，提出了採用規則基專家系統的方法，該模式識別方法具有便於擴展、修改和識別率高等特點。
  10. The plug - in cards provide dual form - c relays, quad form - a, or either quad sinking or quad sourcing open collector logic outputs

    插入式插件提供兩芯form - c繼電器5a四芯form - a繼電器3a或者陷流和源流集電極開路邏輯輸出。
  11. In this way, a simple and direct relation was build up between logical transitions and dynamic current, which makes possible iddt testing pattern generation on logical level

    該方法在電路邏輯跳變與電路動態電流之間建立了一種簡單直觀的關系，使得動態電流測試產生能夠在邏輯級上得以實現。
  12. Experiment results show that this algorithm can identify static crosstalk that destroy circuits function and provide accurate information for ic back - end optimization

    實驗表明，通過驗證噪聲幅值和寬度指標，演算法準確地識別出對電路邏輯功能產生影響的靜態串擾噪聲，為ic設計的後端優化提供了準確信息。
  13. By exploring the characters of dynamic power supply currents of digital circuits using spice, this paper analyzed the relation between iddt and the switching activities when a circuit changes from one logical state to another

    本文通過spice實驗研究數字電路動態電流的特性，分析了數字電路的動態電流與電路邏輯狀態轉變之間的關系。
  14. Traditional static crosstalk identification methods identify crosstalk targets only using coupling capacitance and noise amplitude information, which lead to the pessimistic results and induce a long time to ic design convergence

    摘要傳統的靜態串擾噪聲識別演算法只驗證耦合電容和噪聲幅值信息，沒有考慮噪聲寬度對電路邏輯功能的影響，所以給出的結果過于保守，導致設計收斂的時間被延長。
  15. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  16. Describes the design and realization of partial run - time reconfigurable fpga in detail. in order to reduce the affect of the reconfiguration time on system execution time, mostly static circuit design method in logical design stage and incremental routing method in component implementation stage are proposed. the fft parallel processing algorithm is examined through vvp platform

    本章詳細闡述了基於vvp平臺的多sharc功能插板的具體硬體實現，以動態重構fpga設計為核心，論述了局部動態重構fpga設計流程和方法，提出了極大靜態電路邏輯設計方法和遞增式布線方法，以達到減小動態重配置時間，提高系統運行效率的目的。
  17. Therefore it comes true the on - line adjusting, real - time control and so on. it sames as real locale. the software of logic protect ( include electric logic ) and control includes some usual algebraic and operation model of thermal control and logic operation of logic protect. it adopts foxboro ' s dcs as a example, so we configuration via filling table, user only define i / o condition, fill certain operation variable, and name logic variable. the software offers a friendly user ' s interface, personnel can compile and modify the control and logic program, change the value of logic and control variable conveniently, attach themselves to run, debug and control the set, not need to know about the inside of the old programs deeply. so the configuration software offer a flat that control engineer can attend to the structure of control loop and logic protect ( include electric logic ), not but to handle complicated program

    它以foxboro的dcs控制系統為主要參考模式，採用填表的方式進行控制組態，用戶只需定義i / o條件、填寫具體的運算變量名、邏輯變量名即可。本軟體為建模人員提供了一個友好的用戶界面，使建模人員在建模時不必對模塊內部的控制、邏輯程序有很深的了解就可以方便的對其進行編寫和修改，實時改變各邏輯和控制變量在數據庫里的值，參與運行和調試，從而實現對機組的控制。因此，本組態軟體提供的這樣一個平臺，讓控制工程師能集中精力于控制迴路及邏輯保護（包含電氣邏輯）的構成，而不必拘泥於一些具體而煩瑣的程序操作。
  18. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。
  19. In this course, we study low - power computer design techniques involving mos circuits, logics, computer organization, function units, pipeline, bus protocols, memory subsystems, compiler, os, and virtual machines

    本課程中，我們將研讀計算機低功耗設計技術，內容涵蓋mos電路，邏輯，計算機組織，功能單元，管線處理，匯流排規約，記憶體子系統，編譯器，作業系統，及虛擬機等的相關設計。
  20. With its excellent stability and powerful functions, plc is now widely used in manufacture industry, electric power field, traffic field and etc. many old types of equipment adopts the control system with circuit boards and relays, it ' s in dire need of a new control system to updating the old one

    可編程式控制制器（ plc ）是以繼電器邏輯控制系統為基礎，逐步發展為以處理器為中心，同時具有各類運算、控制、網路等功能的控制系統，憑借良好的穩定性和強大的功能，使得在製造工業、電力、運輸等領域有著廣泛的應用。
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