非邏輯常數 的英文怎麼說
中文拼音 [fēiluóchángshǔ]
非邏輯常數
英文
nonlogical constant-
I believe that it ' s very useful for computer science students who learning boolean algebra and predicate logic ( like my self )
我相信對于學習布爾代數學和謂詞邏輯的計算機科學學生（像我自己這樣的）來說它是非常有用的。This program creates truth tables from boolean expressions. i believe that it ' s very useful for computer science students who learning boolean algebra and predicate logic ( like my self )
這個程序從布爾表達式中創建真實的表格。我相信對于學習布爾代數學和謂詞邏輯的計算機科學學生（像我自己這樣的）來說它是非常有用的。Many mature technologies on this level have been brought out, such as the relational algebra law, the improved logical query plan, the cost estimation of operation, the selective plan based on cost and order of joint, etc. although many methods have been tried out, no remarkable result or noteworthy technology has come to reality because of complexity of data decomposition and network effects
例如，從物理查詢計劃的底層磁盤輸入輸出到語法分析階段的語法分析樹、用於改進查詢計劃的代數定律、邏輯查詢計劃的改進，以及操作代價的估計、基於代價的計劃和連接順序的選擇等全過程，都進行了不懈的努力。在這方面的研究已經非常成熟。In general, comparisons on string columns without blank padding comparison semantics need to be evaluated locally, unless the query compiler is able to find functions to enforce similar logic remotely
通常，不具備空白填充比較語義的字元串列上的比較需要在本地計算，除非查詢編譯器能夠發現在遠程強制類似邏輯的函數。Smpdca architecture has six outstanding excellences : complexity of the control logics of smpdca is lower than large scale superscalar ; supplying shortest inter - processor communication latency using the shared li data cache ; no cost to maintain cache coherence ; hit rate of data cache increase ; easy to reuse many softwares of symmetric multiprocessor ( smp ) ; exploit the parallelism of applications from many levels. this paper present the architecture model of smpdca, and illustrated its function units, and discussed its key techniques, and analyzed the address image policy of multi - ported cache
Smpdca結構具有六個突出優勢：相對于大規模的超標量結構而言， smpdca結構的控制邏輯復雜性明顯要低得多；相對于通過共享主存來實現處理器之間的通信的結構而言，通過一個共享的第一級數據cache來實現處理器之間的通信的smpdca結構能夠提供非常小的處理器之間的通信延遲；沒有cache一致性維護開銷；數據cache命中率提高；便於smp （對稱多處理器結構）的軟體重用；從多個層次上開發程序的并行性。Deductive database is introduction to knowledge and inferring mechnism in artificial intelligece in traditional database. studying it needs very strict theory model as background. relation model and datalog model can describe world
演繹數據庫是人工智慧中的知識及其推理機制在傳統數據庫中的引入，對它的研究需要有非常嚴謹的理論模型為背景，它用關系模型（描述事實）和datalog模型（描述規則）來描述世界，演繹數據庫中主要採用一階謂詞邏輯表示。In practice, providing update and delete access to logical views is difficult and is not fully supported by any current database
在現實中，提供更新和刪除訪問邏輯視圖是非常困難的，當前任何數據庫都不能完全支持。Both are used to separate the responsibility for rendering pages from the model and controller. both accept objects passed into them as an input argument, both allow inserting string values within code " expressions ", and allow direct use of java code to perform loops, declare variable, or perform logical flows " scriptlets ". both are good ways of representing the structure of a generated object web page, java class, or file while supporting customization of the details
Jet與jsp非常類似：二者使用相同的語法，實際上在後臺都被編譯成java程序；二者都用來將呈現頁面與模型和控制器分離開來；二者都可以接受輸入的對象作為參數，都可以在代碼中插入字元串值（表達式） ，可以直接使用java代碼執行循環、聲明變量或執行邏輯流程式控制制（腳本） ；二者都可以很好地表示所生成對象的結構， （ web頁面、 java類或文件） ，而且可以支持用戶的詳細定製。Such enterprise sites must co - exist on the same infrastructure, sharing as much data and business logic as possible, so that the management of the overall operation does not become prohibitively expensive to the selling organization
這樣的企業站點必須共存於同一基礎架構中，盡可能多地共享數據和業務邏輯，以便全部操作的管理對于銷售組織不會變得非常昂貴。The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation
在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。We already know that in a very real sense mathematics is " incomplete. " kurt gdel showed in 1931 that no system of mathematical logic was complete in the sense that it could be self - contained, consistent, and complete
我們已經非常清楚地知道數學是「不完整」的。 kurt gdel於1931年指出，在自我包含，一致性，和完整的意義上，沒有任何數學邏輯系統是完整的。分享友人