高速乘法器 的英文怎麼說

中文拼音 [gāosùchéngfǎqì]
高速乘法器 英文
fast multiplier
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 法 : Ⅰ名詞1 （由國家制定或認可的行為規則的總稱） law 2 （方法; 方式） way; method; mode; means 3 （標...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  • 法器 : [宗教] musical instruments used in a buddhist or taoist mass
  1. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  2. Different from general microprocessors, dsps have harvard architecture or enhanced harvard architecture and units of dsps can work in parallel. to perform multiplication in high speed, dsps also include hardware multiplier in its cpu

    與通用微處理器不同，數字信號處理器採用了哈佛總線結構或改進哈佛總線結構，具有高度的并行性，為了快速完成乘法計算在cpu中增設了硬體乘法單元。
  3. Combining the principles of pipelining and parallelism of dsp with idct theory, we concentrate on the use of multiply - accumulate unit of mcf5272 by merging the operations of addition and multiplication, and realize two dimension of idct with one dimension of idct efficiently. testing shows the software meets the requirement of real - time decoder

    重點結合mcf5272的流水線操作和并行操作特徵和反離散餘弦變換演算法原理，將的二維反離散餘弦變換轉換成8點的一維反離散餘弦變換，利用乘法累加器合併加法運算和乘法運算高效快速地實現了反離散餘弦變換演算法。
  4. The high speed mcu c8051f120 includes a multiply and accumulate engine ( mac ) which can be used to speed up mathematical operations, design control, display circuit and process data

    選用高性能單片機c8051f120 ，利用其帶有硬體乘法器、運行速度高等優點，設計控制及顯示電路，進行數據處理。
  5. Gives techniques for improving the speed of matrix multiplication by more than a factor of two on superscalar risc processors

    講述在超標量risc處理器上用大於二的因子來提高矩陣相乘的速度的方法。
  6. In addition, several way are adopted to optimize the one dimensional transform architecture. improving the architecture resulting from the standard lifting scheme reduces the critical path delay ; an embedded boundary extension algorithm is adopted instead of the standard symmetric extension and it ’ s easier to implement ; the pipeline technique is adopted to increase the speed of processing ; coefficients of the multipliers are transformed into csd forms and the multiplications are substitute by minimum shift - add operations

    改進了由標準的提升演算法得到的變換結構，減小了關鍵路徑上的延時;採用內嵌的邊界延拓來代替標準的對稱延拓，實現更加簡單;採用流水線技術顯著提高了處理的速度;把乘法器系數表示為csd形式，將常系數乘法優化為最少的移位加操作。
  7. A novel and generic approach is presented to the hardware implementation of the rsa cryptoprocessor in deep submicro technology with a redesigned systolic array

    長比特1024位以上數據的全局信號傳輸和乘法器的動態分割問題，對于rsa密碼處理器的速度提高是非常重要的因素。
  8. It is proved by its performance analysis and experimental results that the utilization of processors is increased, that all processors have better load balance. therefore the efficiency of computing scalar multiplication is heightened

    其演算法性能分析和實驗結果證明:改進演算法可提高處理器的利用率，保證各處理器單元具有較好的負載均衡特性，從而加快標量乘的計算速度。
  9. Montgomery multiplication algorithm is optimized for large - bit modular multiplication and vlsi implementation. it is combined with the r - l right to left binary method to achieve speed improvement. special efforts are focused on the problems with long - bit modular arithmetic

    介紹了採用蒙哥馬利模乘法演算法和指數的從右到左的二進制方法，並根據大整數模乘法運算和vlsi實現的要求進行改進的rsa處理器，在提供高速rsa處理能力的同時，可抵抗某些定時分析攻擊和功耗分析攻擊。
  10. The chinese remainder theorem technique increases the decryption data rate by a factor of four. two redundant blocks are added to adapt to the online partition of the multiplier and the variation of the length of

    中國剩餘定理crt的採用，將解密速度提高了近4倍，作者提出一種冗餘結構，使得在採用crt時乘法器可以有效的進行動態分割。
  11. This paper has studied and set up a supervision and control system based on the backing item of jinzhou yangtze river bridge with main span of 500m, by analyzing the development of construction control of cable - stayed bridges in china and abroad, foreword calculation of 250 work cases of plane bar fem, adoption of advanced equipment and devices, quick analysis of gathered data research of karemen filtering method, least square and gray model gm ( 1, 1 ) into the identification of the real state and precuts and effective manage mechanism

    本文以荊州長江公路大橋主跨500米的混凝土斜拉橋施工為應用背景，通過分析目前國內外大跨度混凝土斜拉橋施工控制現狀，結合該橋施工實踐，運用平面桿系有限元計算理論對大橋250個工藝進行正裝計算，採用先進測試設備和儀器，利用計算機快速分析處理技術對現場監測系統收集的數據進行誤差分析，系用卡爾曼濾波法、最小二乘法和灰色理論gm （ 1 ， 1 ）進行結構真實狀態的識別和後期預測，通過科學高效的監控管理機制的運行和監控實踐，探索並建立了一套適合於大跨度混凝土斜拉橋的施工監測監控體系。
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