高速加法器 的英文怎麼說

中文拼音 [gāosùjiāfǎqì]
高速加法器 英文
high speed adder
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 法 : Ⅰ名詞1 （由國家制定或認可的行為規則的總稱） law 2 （方法; 方式） way; method; mode; means 3 （標...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  • 法器 : [宗教] musical instruments used in a buddhist or taoist mass
  1. Research show that wavelet varied - grid feature vector is characterized by high - stable and high - distinguish. based on this vector the apery cognitron has solved the harmony of single - classifier and multi - classifier and the harmony of multi - feature. the data shows that the recognition rate and reliability has been effective improve

    實驗數據表明，小波變網格特徵向量具有穩定性高、區分性強的特點，基於此的智能字元識別機解決了單、多分類器協調和特徵協調問題，在應用快速二值化方法加強處理實時性的同時有效地提高了車牌字元的識別率和識別可靠性。
  2. When high - bandwidth star sensor measurements are available, according to the singer tracking model, the full angular acceleration is modeled as a first order markov process while the use of the attitude dynamics is totally avoided

    在能夠獲得高頻星敏感器測量的情況下，針對模型不確定問題，提出了一種基於singer模型的新的濾波演算法，把角加速度建模為一階馬爾科夫過程，從而避免了使用姿態動力學模型。
  3. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  4. According to the guidline, two nd : yag lasers have been designed and set up, one is end - pumped by lower output power ld using a selfoc micro lens, and the other is end - pumped by high output power ld using a pair of lenses are designed, and the characteristics such as output power and power stabilization of both solid - state lasers are investigated. thirdly, when an empty liquid crystal cell is inserted in the cavity of the nd : yag laser pumped by high power ld, the laser can operates in single axial mode. finally, according to the relationship between the laser output power and the longnitudinal a ld - end - pumped nd : yag laser sensor for displacement measurement has been investigated theoretically and demonstrated experimently, the results indicate that when the mean radius of pumping inside the laser cavity is far less than that of the oscilating laser mode, the exponential of the output power is a gauss function of the longitudinal positon of focused spot of ld pumping beam, both the measurement range and the sensitivity are dependent on the incident pumping power, as the incident pumping power is increased, the measurement range is enlarged and the sensitivity is improve d

    本文首先介紹了ld泵浦nd ： yag激光器的發展狀況、主要特性及其應用，從四能級速率方程出發，推導了ld泵浦nd ： yag激光器的閾值、輸出功率和斜效率的表達式，並簡述了激光器的工作原理、結構型式和倍頻方法；其次，以空間相關的速率方程為基礎，提出了ld端面泵浦nd ： yag激光器的設計方法，給出了一定泵浦耦合方式下，振蕩光模尺寸、最佳輸出耦合率、泵浦光模尺寸、泵浦光焦斑位置等參數的選取依據，以此為依據，設計了自聚焦透鏡耦合小功率ld泵浦nd ： yag激光器和透鏡組耦合高功率ld泵浦nd ： yag激光器，對激光器的輸出功率和功率穩定性等特性進行了實驗研究；再次，在帶尾纖輸出的高功率ld泵浦nd ： yag激光腔內插入一隻空液晶盒，觀察到了激光器以單縱模運轉；最後，根據泵浦光焦斑端面位置對激光輸出功率的影響規律，提出了ld端面泵浦nd ： yag激光位移傳感新方法，並進行了理論和實驗研究，研究結果表明：當激光晶體內泵浦光平均光斑半徑遠小於振西安理工大學碩士學位論文蕩光束腰半徑時，激光輸出功率的自然指數與泵浦光焦斑的縱向位置成高斯變化規律，測量范圍和靈敏度依賴于泵浦功率，隨著泵浦功率的增加，測量范圍擴大，靈敏度提高，當端面泵浦功率為7 . 24w （最大輸出功率為1 . 926w ）時，激光位移傳感器的測量范圍和靈敏度分別是13 . 045mm和0 . 148mw / pm 。
  5. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  6. A method of fuzzy optimization design based on genetic algorithm is presented as a new method of parameter optimization design for dc double closed loop speed adjusting system. the method covers three steps. firstly, speed overshoot rate and settling time are chosen as performance indice according to the demand of engineering. these indice are normalized by using fuzzy membership function and then weighted to form objective function of optimization model of the system. secondly, the dynamic response curve of the system with corresponding parameters and peoformance indice are obtained by computerized numerical calculation and simulation. finally, parameters of engineering design are expanded as searching space ; and parameters of speed regulator and current regulator are taken as genes in chromosome. these genes in searching space are optimized to get best solution by way of genetic algorithm. as shown by experimental results, the parameters designed by this method are capable of significantly improving performance indice of the system, which proves that it is a practical and effective method

    提出一種基於遺傳演算法的直流雙閉環調速系統參數優化設計方法.根據工程技術的要求，選用速度超調量和過渡時間作為參數優化性能指標.將該指標用模糊隸屬度函數歸一化，再加權平均形成系統優化模型的目標函數.採用計算機數值計算方法，通過模擬獲得系統對應參數的動態響應曲線及其性能指標.最後以工程設計的參數為搜索范圍，以速度調節器和電流調節器的參數為染色體中的基因，通過遺傳演算法在搜索范圍中優化這些基因，獲得優化解.實驗結果表明，所設計的參數能使系統性能指標有顯著提高
  7. Pipelining, superscalar organization and caches will continue to play major roles in the advancement of microprocessor technology, and if hopes are realized, parallel processing will join them

    在微處理器技術的發展中，流水線操作、超標量體系結構和高速緩沖內存儲器仍將扮演著重要的角色。如果可能，平行處理方法也會加人。
  8. Combining the principles of pipelining and parallelism of dsp with idct theory, we concentrate on the use of multiply - accumulate unit of mcf5272 by merging the operations of addition and multiplication, and realize two dimension of idct with one dimension of idct efficiently. testing shows the software meets the requirement of real - time decoder

    重點結合mcf5272的流水線操作和并行操作特徵和反離散餘弦變換演算法原理，將的二維反離散餘弦變換轉換成8點的一維反離散餘弦變換，利用乘法累加器合併加法運算和乘法運算高效快速地實現了反離散餘弦變換演算法。
  9. By establishing factories in pakistan, chinese enterprises would cash in on the geographic advantage in terms of exporting to the middle east and africa, he pointed out. bilateral trade between china and pakistan has been enjoying fast growth since 2000, and pakistan has grown into china s second - largest trade partner in south asia following india. the two countries chalked up a record trade volume of some us 3. 06 billion last year, an increase of 26 per cent

    回顧曾經一度流行的增加配置不加價加法或者大幅增加配置營銷，比如企業把許多選裝件變成了標準配置， abs緩速器電動天窗倒車雷達真皮座椅和液晶顯示等配置統統變成了標準配置，藉此提高產品形象，維護企業價格體系，最終這種加法營銷並沒有給企業帶來實際收益和產品形象的提高，加法營銷便草草收場。
  10. Based the methods, the controller may implement high speed cutting

    根據這些方法實現的控制器可以實現高速加工。
  11. At the same time, it detailed demonstrate and carry out the way, which apply housing electric spindles at generation state to carry out housing toque loading in the joint testing and indirectly estimation housing torque loading by the electromagnetism torque of inner tube electric spindles. thus, the technical problem that the high speed shafting torque loading device and torque sender are difficult to ins tall is solved. and it saves a set of expensive high speed shafting torque loading and measuring device

    同時，詳細論證並實施了採用外套電主軸工作在發電狀態實現接合試驗的外套扭矩加載和通過內套電主軸的電磁轉矩來間接估算外套加載扭矩的方法，從而解決了高速軸系扭矩加載裝置和扭矩傳感器不宜安裝的技術難題，並且節省了一套昂貴的高速軸系扭矩加載和檢測裝置，該成果填補了國內高速單向軸承試驗臺扭矩加載領域的空白，達到了國內領先水平。
  12. With regard to the flow regulation of the best - effort traffic, the controllable traffic in high speed computer communication networks, the present paper proposes a novel control theoretic approach that designs a proportional - integrative ( pi ) controller based on multi - rate sampling for congestion controlling. based on the traffic model of a single node and on system stability criterion, it is shown that this pi controller can regulate the source rate on the basis of the knowledge of buffer occupancy of the destination node in such a manner that the congestion - controlled network is asymptotically stable without oscillation in terms of the buffer occupancy of the destionation node ; and the steady value of queue length is consistent with the specified threshold value

    本文從控制理論的角度出發，針對計算機高速網際網路中最大服務交通流即能控交通流的調節問題提出了一種基於多速率采樣的具有比例積分（ pi ）控制器結構的擁塞控制理論和方法，在單個節點的交通流的模型基礎上，運用控制理論中的系統穩定性分析方法，討論如何利用信終端節點緩沖佔有量的比例加積分的反饋形式來調節信源節點的能控交通流的輸入速率，從而使被控網路節點的緩沖佔有量趨于穩定;同時使被控網路節點的穩定隊列長度逼近指定的門限值。
  13. In addition, several way are adopted to optimize the one dimensional transform architecture. improving the architecture resulting from the standard lifting scheme reduces the critical path delay ; an embedded boundary extension algorithm is adopted instead of the standard symmetric extension and it ’ s easier to implement ; the pipeline technique is adopted to increase the speed of processing ; coefficients of the multipliers are transformed into csd forms and the multiplications are substitute by minimum shift - add operations

    改進了由標準的提升演算法得到的變換結構，減小了關鍵路徑上的延時;採用內嵌的邊界延拓來代替標準的對稱延拓，實現更加簡單;採用流水線技術顯著提高了處理的速度;把乘法器系數表示為csd形式，將常系數乘法優化為最少的移位加操作。
  14. This is also a feature of adder circuits and alus that permits these devices to “ look ahead ” to anticipate that all “ carries ” generated are available for addition

    先行也是加法器電路和運算器的一種特性，它允許加法運算時對所有產生的進位預先處理，以利於提高加法運算的速度。
  15. The primary contents and innovations of this article are introduced below. in order to take advantage of the high speed of calculation, and at the same time, improve the accuracy and dynamic - range of the algorithm, three kinds of multi - input floating point adder algorithm ( fpa ) are summarized and a high - performance multi - input fpa structure is put forward with a self - defined floating point format. the performance of the high - performance structure on calculation speed and logic resource consuming is better than the normal structure

    論文的主要工作及創新點如下:為了充分利用fpga處理速度快的特點，同時盡量提高演算法的精度及動態范圍，本文在對浮點加法器演算法進行深入研究的基礎上，規納總結了三種不同的多輸入浮點加法器演算法，並創造性地提出了一種高效的多輸入浮點加法器結構及一種適合於fpga實現的自定義浮點數格式，這種高效的結構在所需的邏輯資源和運算速度上均遠優于傳統的多輸入結構。
  16. First of all we discuss the model of information purifying and bring forward the methods of setting up the according fuzzy set and subject function. secondly after analyzing the traditional technology and the strongpoint and the shortcoing of information purifying we improve it combining with the technique of fuzzy mode identifying, data warehouse, cache etc. and we can perpetrate an on - line and synchronous purifying through analyzing the text and picture showing in the pages of network. finally, we choose sql server 2000 to design the url database and delphi, wingate as the tool for system development to develop an efficient system of information purifying which can keep the network consumer especially young student apart from the intrusion of unfriendly information and make the environment of network pure and fine

    本文首先探討了該系統中的信息「凈化」模型，提出了模型中的模糊集及隸屬函數的構造方法；然後分析了傳統的信息「凈化」技術及其優缺點，結合模糊模式識別、數據倉庫、高速緩存等技術對傳統的信息「凈化」技術進行了改進，改進后的信息「凈化」技術可通過分析正在顯示中的網頁文字、圖片內容，做即時、同步性的網頁內容篩選；最後，利用sqlserver2000設計了url數據庫，選擇delphi 、 wingate作為系統開發工摘要具，設計開發了一種高效的網路「凈化」器，使網路用戶尤其是青少年學生遠離非友善信息的侵擾，讓網路環境更加純凈、美好。
  17. The digital correlators of the two structures are designed with the foundation series 3. 1 xlinx design tools software. the classical structure emphasizes on the design of the adder, whose general form and 3 - 2 compressor structure are designed and analyzed. in this system, an express addition method is put forward, and its synthesis performance proves that it is superior to the two structures mentioned above

    文中利用xilinx公司的foundationseries軟體，詳細設計了兩種結構的數字相關器，經典結構的數字相關器以加法器的設計為重點，設計並模擬了一般結構和3 - 2壓縮結構的加法器，針對本系統文中還提出了一種快速計算加法的設計思想，綜合后比前兩種結構在性能上有明顯的提高；修正結構的數字相關器是基於模塊化的思想設計實現的，並以一個碼元的不同延時點為例，詳細分析了相關器的性能。
  18. Ieee j. solid - state circuits, 2003, 8 : 689 - 695. 10 alvandpour a et al. a 2. 5ghz 32mw 150nm multiphase clock generator for high - performance microprocessor

    模擬結果顯示，在0 . 18m cmos工藝下，這種加法器的延時為485ps ，平均功耗僅為25 . 6mw ，達到了高速低功耗的目標。
  19. Warning : there is no valid license for ase server product. server is booting with all the option features disabled

    可是我在另外沒有做雙機的服務器上用同樣的方法加默認高速緩存確沒有問題！
  20. 2. with a view to the theory of dds, this paper introduces the realization of dds, which based on programmable device. it also discusses in detail some key techniques such as the design of high speed phase accumulator and ram

    2 .從dds的原理出發，著重介紹了一種自行設計的基於可編程邏輯器件fpga的dds電路的實現方法，並對其高速相位累加器、 ram查找表等關鍵技術進行了詳細討論。
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