高速總線 的英文怎麼說

中文拼音 [gāosùzǒngxiàn]
高速總線 英文
hsb high-speed bus
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 總 : Ⅰ動詞（總括; 匯集） assemble; gather; put together; sum up Ⅱ形容詞1 （全部的; 全面的） general; o...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  1. The procedure functions in the compare between partial image of dynamic collection and corresponding image of the airscape. in chapter 5, basing on the analysis of correlative theory of digital image, we introduce the improved fasted - down algorithm and simulative anneal algorithm, which applies to nn calculation, an d bring forward the unique and effective means, correlative original value evaluation. basing on the combination of correlative arithmetic, a stable, high - speed and exact correlative arithmetic is formed, which makes it possible to apply computer vision detection of single - needle quilting in industrial production

    本文展開研究並取得一定成效：構建了基於pci總線的微機實時圖像採集系統；在採集的布料總圖（鳥瞰圖）的基礎上，通過數字圖像的數字濾波、圖像增強、邊緣檢測等處理，提取布料圖像的邊緣，對輪廓的矢量化的象素點進行搜索，得到相應的圖案矢量圖，從而確定絎縫的加工軌跡，生成加工指令；在進給加工過程中，主計算機對動態局部圖像與總圖（鳥瞰圖）的對應部分進行圖像相關的匹配計算，應用數字圖像理論，結合神經網路計算的改進最速下降法和模擬退火演算法，提出獨特而有效的相關迭代初始值賦值方法，形成穩定、高速和準確的相關運算，實現單針絎縫視覺測量和自動控制。
  2. Application of windriver on the development of data sampling card driver

    總線的高速數據採集卡的驅動程序設計
  3. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  4. Vmebus boards have data bus sizes of 16, 32, or 64 bits and are designed to be plugged into a backplane that has up to 21 slots for other boards. these other boards can ben cpu boards or peripheral boards providing various functions. the vmebus standard originated with the motorola versabus in 1979 which was designed using the then new mc68000 microprocessor

    性能的提高主要是由於三個方面的改進： 1 .處理器及高速緩存性能的優化2 .降低內存瓶頸：通過對powerplus體系結構的改進，使內存性能提高到582mb s memory read bandwidth和640mb s burst write bandwidth 3 .系統總線吞吐率的優化：其他的晶元組對pci到內存帶寬只能到70mb s ， powerplus ii則能達到80mb s而無須消耗額外的cpu資源。
  5. This high - speed data acquisition card designed is based on pci bus and have high capacity memory interface. it combines high - speed date acquisition and high capacity real - time memory

    為此，本文設計了一款基於pci總線且具備可擴展大容量存儲設備介面的高速模擬信號採集卡，將高速數據採集和大容量實時存儲結合在一起。
  6. The detailed contents are as follows. through comparatively analyzing design demands in the specifications of countries in the world for the high - speed railway bridges, studying all sorts of structure types of the guideway girder adopted in some country, and summarizing the design outlines of the magnetic levitation guideway girder, the author bring forward a new - style structure of guideway girder : composite steel - concrete structure

    具體研究內容有：通過分析對比世界各國高速鐵路橋梁的設計規范對高速鐵路橋梁的設計要求，研究各國各種磁懸浮試驗線路所採用的軌道梁結構型式，總結磁懸浮鐵路軌道梁的設計要點，提出了一種新型的軌道梁結構型式：鋼?混凝土組合結構軌道梁。
  7. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  8. Through analysising the characteristics of the power system with floating neutral point deeply, the paper puts forward a new plan of single - phase to ground fault line selection on the base of s ' s signal injecton method and gives the hardware and software design. in this design, the high speed sampling and data processing is carried out through using dsp processor ; the large electrice current is drived through the application of a high - performance audio power amplifier and transformer ; the communication between host computer and detectors is realized through rs485 bus technology ; the difference multilevel frequency - selected amplifier is designed and the feeble signal of space is sampled on the base of the theory of magnetic induction ; the interface between dsp and exterior chip and rs485 interface logical is designed through using fpga ; the using of lcd module and keyboard interfacing chip makes the interface between human and machine ; the programme of host computer and detectors is designed through using blocking design method

    在本設計中，採用高速的dsp處理器，實現了對故障特徵信息的高速採集與處理;採用大功率的功放晶元與變壓器配合的方法，實現了大電流信號的驅動輸出;採用485總線技術，組建了裝置主機與多探測器之間的主從式通訊網路，實現了多干擾條件下裝置主機與多探測器的可靠通訊;設計了差分式多級選頻放大電路，採用磁感應的方法實現了對空間微弱信號的接收;利用fpga技術，實現了控制器與多外設的介面及數字信號的串並轉換;採用了先進的lcd液晶顯示模塊及鍵盤介面晶元，設計了人機信息交互的介面;採用了模塊化的軟體設計方法，開發了裝置主機及探測器的軟體程序。
  9. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  10. Tms320vc5402 is a fixed - point digital signal processor, made by texas instruments incorporated, which is 16 - bit word length. vc5402 has enhanced harvard architecture built around one program bus, three data buses, and four address buses for increased performance and versatility

    另外，採用mcs - 51系列cpu作為採集處理卡板載mcu也存在一些比較嚴重的問題，如cpu的指令執行速度慢，總線帶寬窄等缺點，不能完成數據的高速處理。
  11. For high stability of the system, with the realization of hardware of the system, the second part of this paper starts from the transmission line theory, and studies the signal integrity problem of high - speed circuit system in light current. the causes of these signal integrity problems, such as signal delay, reflection, crosstalk, ground bounce noises and etc. are analyzed in theory. combined with actual design, key points of design and standard design flow of general high - speed, high - precision printed circuit board are summarized, which has been applied in actual system, and good effect has been achieved

    為使系統具有較高的穩定性，本文第二部分結合該處理器的硬體實現，從傳輸線理論出發，研究了弱電情況下高速電路印刷電路板中的信號完整性問題；從理論上分析了延遲、反射、串擾以及地彈噪聲等信號完整性問題產生的原因；結合實際設計，總結了一般高速、高精度印刷電路板的設計要點和標準設計流程，並在實際系統中獲得了應用，取得了很好的效果。
  12. Different from general microprocessors, dsps have harvard architecture or enhanced harvard architecture and units of dsps can work in parallel. to perform multiplication in high speed, dsps also include hardware multiplier in its cpu

    與通用微處理器不同，數字信號處理器採用了哈佛總線結構或改進哈佛總線結構，具有高度的并行性，為了快速完成乘法計算在cpu中增設了硬體乘法單元。
  13. Ieee 1394 is a high - speed serial bus standard which supports data speed up to 400mbps, hot - pluggable and has two types of data transfer : asynchronous and isochronous. all these characters make it be considered the first choice of near - term on - board spacecraft architectures for data transfer

    而ieee1394高速串列總線具有支持400mbps的等時和異步傳輸，可熱插拔，使用方便靈活等特性，使其成為未來星載高速總線的首選。
  14. The hardware of system is used sensor and signal conditioning circuit to collect the signal and communication with the computer using the pci2013. for the undulation of temperature and driven current will influence the testing result, they need to be invariableness during testing

    系統硬體以傳感器和相應的信號調理電路作為前向通道拾取被測信號，利用基於pci高速總線的pci2013數據採集卡和串口模塊實現與計算機的數據傳輸和命令通訊。
  15. The committee has produced draft standards for high - speed coaxial cable bus and fiber optic ring local networks

    該委員會已經制定了高速銅線電纜總線及光纖環本地網路標準草案。
  16. Pci bus as a high performance and low price bus is used to design the digital signal process system in this project

    Pci總線作為一種高速總線在課題中被用來設計高性能價格比的數字信號處理系統。
  17. Becausc of using the advanced dsp, popu1ar high speed pci bus and laxge scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree

    由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得本設計的整個系統具有相當的水平。
  18. Because of using the advanced dsp, popular high speed pci bus and large scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree

    由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得整個系統具有相當高的數據處理能力。
  19. North bridge is the center of communication with many high - speed buses and connects cpu, sdram, apg equipment and pci equipment. south bridge is connected to north bridge with pci bus, it has many low speed buses, such as isa, ide, usb, floppy disk, p / s2, serial port, parallel port. with its characteristic, this system has two million ethernet interfaces and one watch - control module

    其中，北橋是整個系統的核心通信部分，含有豐富的高速總線介面，連接了cpu 、 sdram 、 agp設備和pci設備；南橋和北橋通過pci總線互聯，它引出的總線一般速率比較慢，如isa 、 ide 、 usb 、 floppydisk 、 p s2 、串口、並口等。
  20. The manchester decoder with the style of pre - testing and pre - revising can enhance greatly the communication reliability, save efficiently the limited system hardware resources and promote remarkably the system speed

    以預測校正型方式實現的曼碼譯碼器，極大的提高了總線通訊的可靠性，節省了硬體資源，提高了系統的速度。
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