高速計數器 的英文怎麼說

中文拼音 [gāosùjìshǔqì]
高速計數器 英文
high-speed counter
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  • 計數 : count; tally; counting計數卡 numbered card
  1. On one hand, the focal point that the interface circuit is designed lies in lining up the arrangement of the aerial data, have adopted one pair of ports ram to cooperate with the counter and realize the lining up of the data, on the other hand, interface focal point that circuit design transmission of data, part this finish mainly and interface of linkport of dsp, make data transmisst to dsp processor at a high speed, go on follow - up punish

    一方面，介面電路設計的重點在於對天線數據的整理排隊，採用了雙埠ram配合計數器實現數據的排隊，另一方面，介面電路設計的重點是數據的傳輸，這部分主要完成和dsp的linkport的介面，使數據高速傳給dsp處理器，進行后續處理。這個項目按照自上而下的設計流程，從系統劃分、編寫代碼、 rtl模擬、綜合、布局布線，到fpga實現。
  2. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  3. Due to the low mechanical efficiency and long circulating period of the down - charging system of cold bed in bar production line, this paper puts forward the improving project, which adopts ethernet supplemented by dp network, applies the fm350 - 2 advanced counter and suitable maths model and combines the technique of the transducer and hydraulic pressure drive control to realize auto - control

    摘要針對棒材生產線上冷床下卸鋼系統機械效率低、運行周期長，不能適應快節奏生產的現狀，採用以工業以太網為主、 dp網為輔的網路通訊，應用西門子fm350 - 2高速計數器，通過有效的數學計算模型，結合變頻器和液壓傳動控制技術，實現網路自動化控制。
  4. High - performance isolation power supply, magnetism isolation chip and photoelectricity coupler are employed to accomplish high - speed transmission for data, which improve the noise restraint and electric isolation. in addition, the error of measurement of the universal counter is analyzed in this thesis

    使用了高性能的隔離電源、磁隔離晶元和光電耦合器，實現了對計數器的完全隔離，起到了很好的抗干擾效果和電氣隔離作用，可以實現數據高速傳播。
  5. In most acquisition and storage system, it usually caches data on pcb and transfers it to computer by pci to store in the hard disk with fat32 format

    在以往的一些採集存儲系統中，多採用板上高速存儲器緩存，利用pci介面將數據送入計算機完成格式轉換后再存入硬盤中的工作方式。
  6. The application of plc high speed counter in position control

    高速計數器在位置控制中的應用
  7. The application of high speed counter of programmable logical controller

    的高速計數器的應用
  8. Four high - speed counter input

    4個高速計數器輸入
  9. Relay transistor output lcd display 8 function key built - in

    具有高速計數器外部中斷時間中斷模擬輸入輸出萬年歷rtc等功能。
  10. The time is measured by a high - speed counter ; and since t and u are constant, the counter holds a value that is proportional to the input voltage

    這個時間通過一個高速計數器來測量，由於t和u都是常數，計數器所計的數就與輸入電壓成比例。
  11. Utilizing the internal high - rate counter in fx2n series plc and simple external circuit, the author real - timely measures the hydro generator frequency with high accuracy and reliability, which meets the engineering application requirements

    作者利用fx2n系列plc內部的高速計數器和簡單的外圍電路，實現了對機組頻率的測量，滿足了工程實踐中對測頻可靠性、實時性和精度的要求。
  12. There is difference frequency measurement requirement for every part of pid regulating, difference between dynamic quality and static quality in response time and accuracy. according to these, it use the interrupt functions and high - speed counter of the simens s7 - 200 plc cpu226 basic unit and some peripheral circuit to measure frequency ; in software designed, the procedure frame of hydraulic - turbine governor and disperse process of parallel pid are analyzed, an improved pid algorithm is adopted to realize a pid regulation mode with variable structure and parameters ; the mechanical liquid - pressure system of the hydraulic - turbine governor is with electric - hydraulic converter unit of step motor. according to the drive character of five phase of response step motor, a variable frequency regulated voltage driver unit is designed in order to realize interface between plc and driver of step motor

    本文利用s7 - 200plc自身的特點設計了頻率測量單元，根據pid調節各個環節的特點，以及調速器動態特性、靜態特性對頻率測量的實時性和精度要求的不同，利用s7 - 200plc基本單元中內置的高速計數器以及相應的外圍放大整形、分頻電路，實現了水輪發電機組頻率的測量；在軟體上，對微機調速器的整個程序框架、並聯pid的離散化過程進行了分析，選用改進的pid演算法實現了變參數、變結構的pid調節模式；調速器的機械液壓隨動系統具有步進電機電液轉換元件，採用五相反應式步進電機，根據其驅動特性設計了變頻調壓驅動器，實現plc與步進電機驅動器之間數字介面。
  13. Thirdly, the range switch circuit and filter circuit are designed in the analog input channel. to realize the safe high speed acquisition, the interface circuits are separated from the function circuits, and the isolation power with high performance and digital isolator is used to restrain the common mode disturb and noise of the input

    3 .模擬輸入通道設計有量程切換電路和濾波電路，並且採用了屏蔽、浮置技術和磁耦隔離技術，使用了高性能的隔離電源和磁電耦合器，有效地抑制了輸入信號的共模干擾和噪聲，實現了安全、高速的數據採集。
  14. A testbench program is edited to simulate the behavior of the fifo. after the software simulation is accomplished, a real hardware circuit is designed to multiplex two data channels ( 1553b data channel and 1394 data channel ) according to ccsds standard. during the experiment and hardware debugging, the output logic of the fpga is checked up

    設計中，用vhdl語言對高速復接器進行行為級建模，為了驗證這個模型，首先使用軟體進行模擬，通過編寫testbench程序模擬fifo的動作特點，對程序輸入信號進行模擬，在軟體邏輯模擬取得預期結果后，繼續設計硬體電路，設計出的實際電路實現了將來自兩個不同速率的信源數據（ 1394總線數據和1553b總線數據）復接成一路符合ccsds協議的位流業務數據。
  15. In such situation, controlling of the transf - orming process and synchronizing of sampled data only could be achie - ved via hardware, and data must be stored ( by using high - speed stora - ge chip ) and digital signal must be processed ( by using high - speed d - sp ) in real time simultaneously

    在這種情況下，通常只能用硬體實現轉換過程的控制和采樣數據的同步，仔細設計時序電路，同時必須採用高速存儲晶元對數據進行存儲和高速的數字信號處理器（ dsp ）完成數字信號的實時處理。
  16. But what we ' re seeing is that many of these challenges we face in software ? connecting machines together, having parallel algorithms that allow many compute systems to work on a problem and combine their results together ? these problems are very similar to the problems that exist in high - end supercomputing

    但是我們正在看見什麼是多數的這些挑戰我們在軟體?一起連接機器中面對，讓允許多數的平行運演算法則計算系統處理一個問題而且一起聯合他們的結果?這些問題對在高結束高速計算中存在的問題非常相似。
  17. Secondly, basing on single channel if sr receiver mathematic model, this thesis has designed if sr receiver subsystem and brought forward its design project and system circuit principle diagram, and explained the system working principle. furthermore, this thesis introduces the working principles and respective applications of wideband high - speed adc ad6640, ddc ad6620 and high - speed dsp tms320c6713 according with the if sr receiver subsystem high - speed analog digital conversion department, digital down conversion department and high speed digital signal processing department. thirdly, the thesis emphatically demonstrates the software realization department of the if sr receiver subsystem, which including ad6620 ' s inner parameter software setup, tms320c6713 data transmission and processing and the quadrant demodulation algorithm program realization

    其次，基於單通道中頻軟體無線電接收機數學模型，本文設計了中頻（ if ， intermediatefrequency ）軟體無線電接收機子系統，給出了中頻軟體無線電接收機子系統的設計方案和系統電路原理圖，說明了系統工作原理，並分別對應系統中的高速模數轉換部分、數字下變頻部分、基帶數字碩士學位論文軟體無線電理論研究及中頻軟體無線電接收機子系統設計信號處理部分，介紹了高速adcad664o ，數字下變頻器（ ddc ， digitaldownconverter ） ad6620 ，高速數字信號處理器（ dsp ， digitalsignalproeessor ） tms320c6713的工作原理，以及它們在中頻軟體無線電接收機子系統中的應用。
  18. With fpga technology, the speed of the high rate multiplexer is greatly increased. it will be applied in the spacecraft data systems and meet the requirements of the space missions in future

    應用硬體可編程邏輯晶元fpga設計高速復接器，大幅度提高了數據的復接速率，可應用於未來的星載高速數據系統中，能夠完成在軌系統的數據復接任務。
  19. To ensure the precision of distance measuring, the high - speed laser driving circuit and the detect - amplifying circuit constituted by two class high - speed operational amplifiers are used in auto adaptive cruise - control system, and the laser flying time is measured by a sixteen bit ' s binary counter, whose counting frequency is 100 megahertz

    為保障測距精度，裝置採用高速激光器驅動電路和由兩級高速運算放大器構成的探測放大電路，並用一個計數脈沖頻率為100mhz的16位二進制計數器完成激光收發間隔時間的測量。
  20. Advanced fpga technology is introduced to improve the integration of digital circuits, and all digital circuits in the original module are integrated in the fpga chips, which could not only reduce the cost, but also improve the reliability and measurement precision of the circuits. high speed digital signal processor ( dsp ) is selected as the coprocessor instead of scm ; it can receive all kinds of commands sent from vxi, analyze and execute the commands, harmonize each section of the module and process the data. higher - conversion - speed comparator chip is adopted to convert the input signals being measured into square waveform signals which could be identified by fpga chip ; it can expand the measurement range of frequency dramatically

    本文在原有vxi總線四通道計數器模塊的設計基礎上，通過對原模塊缺陷的分析，採用一些新的技術和新的電子器件來重新設計該計數器模塊:採用最新的fpga技術來提高數字電路的集成度，將原模塊中的所有數字電路全部集成在fpga晶元中，這樣不僅能節約成本，還能提高電路的可靠性和測量精度;採用高速的數字信號處理器（ dsp ）取代原有的單片機作為協處理器，來接收vxi發來的各種命令，分析命令、執行命令、協調模塊各部分的工作以及對數據的處理;採用轉換速率更高的比較器晶元將輸入的被測信號轉換為fpga晶元能夠識別的方波信號，能極大提高測量頻率的范圍;採用d / a轉換晶元和隔離運算放大器得到隔離通道所需的比較電平，該比較電平值能夠根據實際需求進行設置，能增強模塊的使用靈活性。
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