高速邏輯電路 的英文怎麼說

中文拼音 [gāosùluódiànlù]
高速邏輯電路 英文
large artificial nerve network
  • 高 : Ⅰ形容詞1 （從下向上距離大; 離地面遠） tall; high 2 （在一般標準或平均程度之上; 等級在上的） above...
  • 速 : Ⅰ形容詞（迅速; 快） fast; rapid; quick; speedy Ⅱ名詞1 （速度） speed; velocity 2 （姓氏） a surna...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 高速 : （高速度） high speed; high velocity （hv）; high rate; swift; fast; express; high-speed
  • 邏輯 : logic
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. These character based on sichuan power network ' s practice operation experience, in allusion to the config of the carrier wave protection in bypass breaker operating, through the study of protection ' s typical config : one side lfp - 902a, one side csl - 101a, proceeded comprehensive act module test, noted plenty of first hand test data and wave picture, proceeded detailed theory analyses, plenitude demonstration atresic type carrier wave distance protection when twain side atresic type logic is not completely same, basically can fill power network ' s requirement to relay of reliability selectivity speedly and sensitively

    本文結合四川電網的實際運行經驗，針對旁路開關代路運行時的保護配置情況，通過對旁路代路時保護典型配對組合：一側lfp - 902a ，一側csl - 101a的保護配置情況的深入研究，做了全面的動模試驗，記錄了大量的第一手試驗數據和波形，進行了詳細的原理分析，充分驗證了高頻閉鎖式距離零序保護在兩側閉鎖式邏輯不盡一致的情況下，基本能夠滿足電網對繼電保護的可靠性、選擇性、快速性以及靈敏性的要求。
  2. Through the simulation of large - scale circuit simulation proved that use the crossover tearing technology could detailed network structure, simplify the diagnostic process, and the neural network can parallel deal with the diagnosis information, and the logic operation can judge the information of the multi - fault. the illustrative simulation shows that it can increase the diagnosis speed and decrease the workload before test

    通過對大規模模擬電路的模擬證明，使用交叉撕裂明細網路結構，簡化診斷過程，且運用神經網路組對信息進行并行處理，邏輯分析運算對多故障信息進行處理判斷，大大提高了故障診斷速度，減小了測前工作量。
  3. This thesis focuses on the ingress process module of ctu, which translates c - 5 dcp format to rainier 4gs3. the specification analysis, architecture and logic design, functional simulation testbench design, synthesis report and testing result are discussed in this thesis. the research work mainly includes : the specification analysis and design requirements of ctu logic ; the architecture and logical design of ingress process module, which includes receive control fsm, send control fsm and cell position adjustment logic ; the performance improvement of ingress process module to receive and transmit data cell at the full line speed

    本論文的主要研究工作包括：通信協議轉換邏輯的功能分析和設計需求；通信協議轉換邏輯上行方向的系統分析及體系結構設計，包括上行接收狀態機、發送狀態機、信元內位元組位置調整機制等的設計；通信協議轉換邏輯上行方向的線速設計，主要是上行接收的線速設計，要使用流水設計技術；提出了高速實現roundrobin調度策略的實現方法，並設計實現了桶式移位器和優先級編碼電路；應用bfm模擬模型設計了上行處理各模塊的模擬testbench ，完成了各級模塊的模塊模擬和系統集成模擬。
  4. 2. the high performance realization rules and experiences are discussed at the level of micro - architecture, logic and layout respectively

    2 ）分別在結構級，邏輯級和版圖級分析了高速數字電路的高速解決方案。
  5. The hardware of the system is composed of a high - speed optical - isolator circuit, a first - in / first - out dual - port memory buffer circuit, a pci interface chip ql5032, and a logic control circuit

    系統的硬體部分是由高速光電隔離電路，雙埠fifo存儲緩沖電路， pci總線介面電路ql5032及邏輯控制電路等組成。
  6. As a result, this design accomplishs the function of circuit, which not only can satisfy the high speed image data transmission of large screen system and improve the performance of circuit, but also increase the flexibility of circuit design. in the design, it is possible to act hardware description language procedure according to the practical application demand, instead of revising hardware design of the circuit, which reduce the design cycle and the cost

    所以，本課題運用可編程邏輯器件來完成電路功能，不僅能夠滿足大屏幕系統高速圖像數據傳輸對速度的要求，改善了電路性能，而且增加了電路設計的靈活性，設計中可以根據實際應用的需求靈活修改相應硬體描述語言程序，而不需要修改電路硬體設計，縮短了設計周期，降低了成本。
  7. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  8. With high speed and large - scale integration of electronic circuits, boolean algebra is insufficient to describe the complicated logic behavior of digital circuits

    近些年來，隨著電子電路的高速化和大規模集成化，布爾代數作為描述數字電路的邏輯行為的工具，越來越顯示其不足
  9. A testbench program is edited to simulate the behavior of the fifo. after the software simulation is accomplished, a real hardware circuit is designed to multiplex two data channels ( 1553b data channel and 1394 data channel ) according to ccsds standard. during the experiment and hardware debugging, the output logic of the fpga is checked up

    設計中，用vhdl語言對高速復接器進行行為級建模，為了驗證這個模型，首先使用軟體進行模擬，通過編寫testbench程序模擬fifo的動作特點，對程序輸入信號進行模擬，在軟體邏輯模擬取得預期結果后，繼續設計硬體電路，設計出的實際電路實現了將來自兩個不同速率的信源數據（ 1394總線數據和1553b總線數據）復接成一路符合ccsds協議的位流業務數據。
  10. In the hardware design, the analog circuit, high - speed a / d convertor, storage control logic and vxibus interface are discussed. the results of the simulation and analysis of the circuits are given

    在模塊的硬體電路設計部分中，著重對信號調理電路、高速a / d轉換器、高速存儲邏輯控制以及vxi總線介面等內容進行了討論，給出了具體的電路設計和關鍵器件的說明，並對部分模擬電路和數字電路進行了模擬分析。
  11. Bypass breaker usually operate instead of line breaker in power system, considering the type of bypass breaker ' s carrier wave protection is different from the one of line versus side carrier wave protection, both protection ' s theory and stop signal, send signal logic have got differentiate, in order to ensure power network stabilize operation, line rapid protection must be run, so it is necessary to validate from protection theory and proceeding test the internal fault condition that the protection in both side of the line is different

    電網中經常出現旁路開關代線路開關運行，由於旁路高頻保護和線路對側高頻保護型號不一致，保護原理和停信、發信邏輯有區別，為了保證電網的穩定運行又必須要求線路快速保護投入運行，這就要求從保護原理上和進行試驗來驗證此時由線路兩側不同的保護裝置構成的高頻保護的動作情況。
  12. In data sampling circuit, high - speed, complex programmable logic device cpld technique is used. high - speed double - port ram, control sampling time sequence logic, cpu interfaces and bus circuit are implemented in cpld. sampling speed is up to 80mhz, sampling depth is ik - byte, and cpld can fulfill the requirement of the software arithmetic to sampling

    在數據採集電路中採用了高速復雜可編程邏輯器件cpld技術，晶元內設計有高速雙埠ram 、控制采樣時序邏輯及cpu介面、總線等電路，采樣速率高達80mhz ，采樣深度1k位元組，很好地解決了超聲波微位移傳感器軟體演算法對采樣的要求，並可實現在線升級，大大提高了系統的整體性能。
  13. In order to make the speed of the function simulation faster, the system adopting vhdl ( very high - speed integrated circuit hardware description language ) to make simulation faster, at the same time this make it easy to transplant the circuit to other kinds of isp chips

    為了提高模擬的速度，對部分電路採用vhdl語言進行邏輯描述。通過實驗證明，在微波測距儀中採用在系統可編程邏輯器件，收到了很好的效果。
  14. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。
  15. The scale, facility, setup mode and the topper application are increasing, but the network management system still adopts a centralizing structure based on manager / agent model. in the centralizing structure, the network management system can ’ t change with the scale and complexity, which made the system bigger and bigger. all management logic is computing in one workstation, that will occupy too many bandwidth, depress performance and made the workstation become the weakest part, if the workstation overrun or dead, agent can ’ t come back because it must wait manager ’ s command

    目前，我國電信網路正處于高速發展中，網路的規模越來越大，設備種類越來越多，組網方式越來越多樣化，應用越來越復雜，但是網路管理系統仍然普遍採用管理員/代理的集中式管理方法，在集中式網路管理模式中，網管系統不能隨著網路規模和復雜度的變化而變化，致使網管系統越來越龐大;網路管理邏輯全部集中在一個管理工作站中計算，需要佔用大量的帶寬來傳輸設備數據，有效性差，同時管理工作站是系統中最脆弱的部分，一旦管理方超負荷或死機，代理方因為必須等待管理方的指令而無法恢復系統，導致系統崩潰。
  16. Based on the requirement of the data storage of aerospace craft, the purpose of this dissertation is to study the high speed solid - state storage technique interface logic with compactflash card array. the design scheme of a suit of high speed solid - state storage system used with ti " tms320vc5402, lattice " isplsi 3448 and sandisk compacflash card are expatiated. in addition, the paper also gives the material realization scheme of the experiment circuit and interface logic simulation analyzing

    本論文以高速cf卡陣列固態存儲技術的介面設計為主要內容，闡述了利用ti公司的tms320vc5402 、 lattice公司的isplsi3448 、 sandisk公司的compactflashcard等組成的高速cf卡陣列固態存儲系統的設計方案，並給出了實驗電路實現方案和介面邏輯的模擬分析。
  17. Design of logic control circuits, device driver and application of the high - speed data communication system based on pci bus are completed. with s5933 bus master ( dma ), bidirectional and high - speed data transmission are realized

    本文完成了基於pci總線的雙機高速數據通信系統的邏輯控制電路設計、驅動程序及應用程序的開發，實現了s5933總線主控（ dma ）方式的雙向高速數據傳輸功能。
  18. Design and implementation of a fast round robin scheduler, in which a pipelined barrel shifter and a pipelined priority encoder are used ; testbench development of functional simulation for module verification and system verification, in which the bfm simulation model are used and some reference examples are proposed ; discussing the questions that should be paid attention to when using fpga to design high speed circuits and some design skills ; taking part in the system ' s integration and fpga implementation ; taking part in the system ' s test and verification ; the design of this thesis has provided some key method for inter - communication among different network processors, and also accelerated the development of communication products

    討論了用fpga設計高速電路應注意的問題和一些常用的設計技巧；參與整個轉換邏輯的系統集成和fpga實現；參與系統的驗證工作；通信協議轉換邏輯的設計不僅可以解決不同網路處理器之間互通的問題，而且對于促進國產數據通信產品的研究與開發具有很重要的意義。同時在設計的過程中，進一步地探討了基於fpga的高速電路設計技術，對于fpga的設計有參考價值。
  19. A mac unit has been specially optimized and can complete a 32 - bit mac operation within one clock cycle of 5ns. we analyze the multiplication procedures and find out the obstacles to improve the speed. to accelerate the multiplication operation, a modified booth structure has been used to reduce the number of partial products

    在分裂式alu設計工作中，提出了三種方法解決時延問題： （一）具體分析關鍵路徑中決定時延的關鍵信號，優化其相關邏輯電路，提高速度，減小模塊整體關鍵路徑時延。
  20. Its intrinsic switching time is very short ; on the order of a picosecond. perhaps even more important is the low power dissipation ; superconducting circuits dissipate on the order of a microwatt per gate, a thousand times less than cmos circuits

    這種數字電子技術具有高速、低功耗的特點，使用基於rsfq技術的邏輯電路的時鐘頻率可達到幾百個ghz ，而功耗只有0 . 3微瓦門。
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