點緩存 的英文怎麼說
中文拼音 [diǎnhuǎncún]
點緩存
英文
point cache-
The control system included the following units : video decode unit, data format conversion unit, fpga controller, cache unit and d / a monitor. the above self - design control unit plus row and column power supply units make the whole fed driving system, thus drove the 25 inch sample and realized color video display. the 25 inch vga sample thus fabricated could display video images, and obtained its brightness 400cd / m2, contrast ratio 1000 : 1, 256 circuit gray scale
本文介紹了fed驅動系統的工作原理，重點論述了基於fpga的vga級彩色fed新型驅動控制系統的研製，這種新型fed驅動控制系統主要包括視頻解碼電路、數據格式轉換電路、 fpga控制電路、數據緩存電路和d / a監控電路，配合后級列灰度調制單元和行掃描單元，組成完整的fed驅動系統，可以驅動25英寸vga級fed顯示屏，實現彩色視頻顯示，樣機亮度達400cd / m2 、對比度為1000 : 1 ，灰度等級為256級。A data acquisition system with the following features is realized : ? transmission rate up to 100kbyte / s over usb ; ? system ' s dynamic range as high as 120 db ; ? multi - kind of trigger mode control ; ? sampling rate as high as 100 ksps ; ? 12 - bit a / d conversion accuracy ; ? 32k bytes on - board data memory ; ? the system, which was made up of large - scale electronic chips, is small, light and portable, and suitable for field use
本設計最終實現了一個瞬態信號數據採集系統，它具有以下特點： ?採用usb介面進行高速數據傳輸，傳輸速度達100kbyte / s ； ?採用浮點a / d轉換技術，動態范圍達120db ； ?多種采樣觸發控制方式； ?最高采樣率100ksps ； ? 12位采樣精度： ? 32kb數據緩存； ?使用新型大規模電子器件，系統結構緊湊，重量輕，適合野外作業。Dynamic indicates that the vertex buffer requires dynamic memory use, which is useful for drivers because it enables them to determine where to place the buffer
表示頂點緩沖區要求動態使用內存，這樣對驅動程序有好處，因為這樣可以使驅動程序確定緩沖區的放置位置。The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too
詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。Specifies use of the memory class for vertex buffers
指定內存類用於頂點緩沖區。The implementation of deltafile 3. 0 can be divided into two modules ? real - time file system module and manage module for both facilities and drives. the real - time file system contains four parts ? system call api layer, file node manage layer, virtual file system layer, concrete file system layer, which perform the abstraction of the facility
實時文件系統模塊包含系統調用api層、文件節點管理層、虛擬文件系統層、具體邏輯文件系統層四部分，主要完成與設備無關的數據存取介面抽象和各種文件系統標準的實現;設備與驅動管理模塊包含邏輯設備管理層、物理設備管理層、設備緩沖區高速緩存層、設備驅動管理層四部分，主要完成外部存儲設備管理及其驅動介面抽象功能。Aspects written in earlier phases of learning tend to focus on auxiliary concerns that can be unplugged from the system and on horizontal concerns that apply across many domains such as transaction management, caching, or tracing
前期學習階段編寫的方面側重於可從系統拔出的輔助關注點和跨許多域應用的水平關注點（比如事務處理管理、高速緩存或跟蹤） 。Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction - level parallelism, reduces data cache pollution, and decreases data cache miss ratio. stack access latency can be reduced by using fast address generation scheme proposed here
該方案將棧訪問從數據高速緩存的訪問中分離出來，充分利用棧空間數據訪問的特點，提高指令級并行度，減少數據高速緩存污染，降低數據高速緩存失效率，並採用快速地址計算策略，減少棧訪問的命中時間。A multimedia proxy server model is proposed based on the layer - encoding model. the server model makes the server ' s cache be used effectively and can adapt the changing of network bandwidth. in the server model, the data quality of a program stored in the server ' s cache, is directly related to the requesting frequency and requested bandwidth of the program
本文提出了一套基於分層編碼模型的多媒體代理服務器模型，該模型能自動適應國防科學技術大學研究生院學位論文工nternet中的帶寬變化，充分利用代理服務器的cache空間，並使cache中緩存的多媒體數據質量與其點播頻率和點播帶寬成正比。However, with many burst traffic simultaneously arriving at a node, the queue length may become larger and buffer overflow in a moment, or high - speed link is emerged into slower one, there will be in congestion
然而，當多個突發業務同時到達一個節點時，緩存隊列長度迅速增加，在極短的時間內出現緩沖溢出，或高速鏈路接入慢速網路中引起輸入鏈路速率大於輸出鏈路速率，則導致網路擁塞。In addition, designing pages and data requests to be cached, particularly in areas of your site where you expect heavy traffic, can optimize the performance of those pages
另外，通過設計要進行緩存的頁和數據請求（特別是在站點中預期將有較大通訊量的區域） ，可以優化這些頁的性能。13 shi l, gu z et al. a ppm prediction model based on web objects popularity. lecture notes in computer science 3614, wang l, jin y eds.,
最後，指出下一步工作的重點是基於ppm的高階預測演算法與緩存策略結合的性能分析和評價以及基於知識網格的預取和緩存的一體化模型研究。Reorders faces to increase the cache hit rate of vertex caches
對面重新排序，以增加頂點高速緩存的高速緩存命中率。The portal automatically determines which aggregated pages can be cached and sets page headers that enable static parts of your site to be projected into caches in reverse proxies or browsers
門戶將自動確定哪些聚合頁面可以緩存，並自動設置頁面標頭以將站點中的靜態部分緩存到反向代理或瀏覽器中。Locks a range of vertex data and returns the vertex buffer memory
鎖定某一范圍的頂點數據，並返回頂點緩沖區內存。Locks a range of vertex data and obtains the vertex buffer memory
鎖定某一范圍的頂點數據，並獲取頂點緩沖區內存。Supports rendering of primitives using vertex data stored in vertex buffer objects
支持使用在頂點緩沖區對象中存儲的頂點數據來呈現基元。So we studied a special structure of crossbar in this thesis, which was called as the buffered - crossbar that can support the switching of variable length packets directly
因此，本文將研究一種特殊結構的crossbar交換背板技術? ?具有節點緩存能力的crossbar結構，以支持對變長分組的直接交換。This results in the vertex buffer you created earlier being bound to source index 0, so any vertex element which is pulling its data from source index 0 will retrieve data from this buffer
上面代碼的執行結果就是把之前建造的頂點緩存榜定到更早之前創建的資源索引0上面，繼而這里所有的頂點元素都可以通過資源索引0來得到他們在緩存中的數據。It is highly recommended that you use index buffers rather than raw application - allocated memory when possible, for the same reasons as vertex buffers
我們強烈推薦你盡可能使用使用索引緩存而不是直接程序分配內存，同樣也推薦使用頂點緩存。分享友人