adder stage 中文意思是什麼
adder stage
解釋
混合級-
Sparse - tree architecture enables low carry - merge fan - outs and inter - stage wiring complexity. single - rail and semi - dynamic circuit improves operation speed. simulation results show that the proposed adder can operate at 485ps with power of 25. 6mw in 0. 18 - mu m cmos process
具有代表性的并行前綴進位結構有kogge - stone樹brent - kung樹han - carlson樹和knowles樹等,一些高性能的加法器也由此被設計出來。
分享友人