array architecture 中文意思是什麼

array architecture 解釋
數組結構
  • array : vt 1 打扮，裝飾。2 使…列隊，排列。3 提出（陪審官）名單，使（陪審官）列席，召集（陪審官）。n 1 整...
  • architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
  1. Second, it do research on the theory of quality of service, such as intserv and diffserv module, qos protocols, qos array techniques and qos architecture. third, based on the current techniques as j2ee, wfe and xml, an architecture of a pbnm system using ejb and wfe is presented. forth, it is discussed for some key components in pbnm domain, such as qos information module, policy based metwork management framework and the relations among components fifth, it designed the relations and communication interface between pbnms and other oss modules, and elaborated a strategy of building a distributed object information model and discussed its specific implementation, and implement the policy hierarchy using domain

    本文的主要研究工作和成果如下：分析了傳統的網路管理技術和發展歷程，對網路管理的國際標準cmip 、 tmn 、 snmp和cops等及網路管理的功能進行了討論；對服務質量（ qualityofservice ， qos ）中的主要理論，如intserv和diffserv服務模型、 qos協議、 qos隊列技術、 qos體系結構進行了探討；基於當今的流行技術j2ee 、 wfe 、 xml ，提出並設計了以ejb wfe框架構築的策略管理體系結構；討論了基於策略的網路管理（ pbnm ）中的若干關鍵技術問題，如策略信息模型、策略網路的系統構架及組件間的交互關系；設計了基於策略的網路管理系統（ policybasednetworkmanagementsystem ， pbnms ）與運營支撐系統（ operationsupportsystem ， oss ）各模塊間的關系和通信介面，運用分佈對象技術建立網管信息模型，運用域進行策略的等級管理；討論了策略服務器（ pdp ）和策略實施點（ pep ）的工作流程，採用關系數據庫進行策略的存儲，設計並實現了策略數據庫、策略服務器（ pdp ） 。
  2. A novel flash memory, which uses the source induced band - to - band tunneling hot electron ( sibe ) injection to perform programming, and a pmos selected divided bit - line nor ( pnor ) array architecture are originally introduced in this dissertation

    本論文首次提出了一種採用源極誘導帶帶隧穿熱電子注入（ sourceinducedband - to - bandtunnelinghotelectroninjection ）進行編程操作的新型快閃存儲器技術和一種pmos選擇分裂位線nor （ pmosselecteddividedbit - linenor ）快閃存貯陣列結構。
  3. The paper puts forward a combined - allocation - scheme based on the idea of constrained - block - allocation at the storing allocation strategy and gives disk - striping about the storing of big capacity disk array. in the study about the access path of the multi - media data, we introduce several kinds of representative multi - dimensions data index structure including k - d tree, r tree, vp tree and so on. ( 3 ) the research of multi - media database system architecture.

    在存儲分配策略上根據受限塊分配（ constrainedblock ? allocation ）的思想，本文提出了聯合分配模式（ combinedallocationscheme ） ；並針對大容量磁盤陣列的存儲給出了條形分配方案（ diskstriping ） ；在多媒體數據的存取路徑的探討中，重點介紹了幾種有代表性的多維數據索引結構，有k - d樹、 r *樹、 vp樹等。
  4. With phased array radar observing target ' s improvement of different performances of the aircraft, the deterioration of the working environment of radar and improvement of the radar demand request more and higher for putting forward the equipment of phased array radar video signal processing. the digital signal processing is all the time the developing direction of radar signal processing, its main shortcoming is that the increase processing precision, and the amount of information at the same time bring on the amount processing redouble, method to solve this problem is the real - time high speed digital signal processing system. presently multi - processors parallel processing is the focus of the field of high - speed real - time processing. this paper ' s background is the high - speed real - time signal processing of phased array radar. a parallel computing system designed with 4 adsp - 21060 analog device inc ' s dsp is presented. lt has fully utilized the dsp ' s characteristic to be supported the parallel computing, and formed a mes h architecture. this paper design and discusses this system in terms of design for test ( dft ) and real time operation system ( rtos ), and have put forward the new solution for the design and development of the high - speed real - time signal processing system. then, analysed the subject matter faced at the same time

    本文以高速實時相控陣雷達視頻信號處理為背景，提出了一種由4片ad公司adsp - 21060構成的并行計算系統。它充分利用了adsp - 21060支持多處理器并行計算的特點構成了一種網格結構，並且從可測性設計、實時操作系統角度對該系統進行了設計與討論，為高速實時信號處理系統的設計與開發提出了新的解決方案，同時分析了面臨的主要問題。本文首先分析了相控陣雷達信號處理單元的特點，然後針對適合於片間并行的adsp - 21060討論了并行計算結構，提出了一種採用四片adsp - 21060構成網格結構的信號處理平臺，分析了它的工作原理。
  5. First, the low testing power dft solution - - scan array architecture are presented. in the scan array, the inserted wrapper and paralleled leaf scan chain reduce the testing power as low as the power dissipation in the normal working mode

    首先，從優化測試功耗的角度出發提出了掃描陣列結構，通過加入wrapper測試控制結構以及構建并行化的分支掃描鏈，有效地將測試功耗降低到與正常工作功耗相當的量級。
  6. This paper describes a test architecture for minimum number of test configurations in test of fpga field programmable gate array luts look up tables

    特別地， fpga適用於這樣一些系統的原型，即其正確操作對于評價新型體系結構是必要的。
  7. This paper presents an architecture based - on shift register array, which can be used for the search for the two search pattern simultaneously. this architecture was inspired by the vlsi architecture for diamond - search - pattern - based algorithms. it exploits the overlap of reference data among the search points to reduce data memory accesses which are the most power consuming operations

    其基本思想是利用搜索點之間的參考數據重疊的特徵，把需要用於多個搜索點計算的參考數據存儲在移位寄存器陣列中，通過移位操作來滿足不同搜索點的計算需要，大大降低了數據存儲器訪問次數，從而減少了運動估計中功率消耗最大部分的操作。
  8. Also we decided the scheme and architecture of eight channels array signal simulation device system on the base of system demand analysis, finished the pcb board design, hardware circuit implementation, driver design

    然後分析系統需求，我們確定了八通道陣列信號模擬器系統的設計方案和體系結構，完成了模擬器的pcb板設計、硬體電路實現和驅動程序設計。
  9. Aimed at the confined condition in this system and the special polarization mode of electromagnetic field in multi - path environment, the architecture with polarization antenna array is proposed

    針對使用環境的限制與多徑環境中電磁極化的特殊情況，提出了利用極化天線陣列構建mimo系統的設計方案。
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