array chip 中文意思是什麼
array chip
解釋
陣列式晶元-
Fcpga flip chip pin grid array
反轉晶元針腳柵格陣列 -
The research object of this thesis is a chip - array that is fixed on one of printed circuit boards ( pcb ), which are located in a forced air field ( forced convection ) in an electronic case ; and from the essential equations of airflow we can deduce the mathematical model of the turbulent flow ; then we can establish the finite element algorithm and apply the fe software to work out the equations of turbulent flow, finally we can use the software to display and analyse the field of flow and temperature
本文以處于強迫空氣對流流場中的某pcb板及其板上的電子元件陣列作為研究對象，推導了紊流流場的數學模型，並建立了相應的有限元求解格式，應用有限元法分析軟體對該系統的紊流流場和溫度場進行了模擬分析：解算出pcb板上各電子元件的溫度分佈；並提出了用於求解系統風道特性曲線的cfd方法。 -
This thesis primarily discussed the baseband processing of ss communication signal based field programmable gate array ( fpga ) asic chip
本論文主要討論和實現了基於fpga的擴頻通信信號的基帶處理。 -
Thiscould be transcriptional binding sites for example. proteins such asfluorescently labeled dna - binding transcription factors in solution areadded to the chip and incubated on the array
這可以轉錄結合位為例.蛋白質等熒光標記dna結合轉錄因子溶液加入關于陣列晶片及孵化 -
First, the domestic status quo of track inspection and the overseas development of track inspection device are introduced in the thesis. based on the introduction, three schemes to monitor the track irregularity by means o f photoelectric inspection technology are put fonvard in the thesis : using photosensitive diode, using ccd array wfth computer, using ccd array with single chip computer
論文首先介紹了國內軌道檢測的狀況和國內外軌道檢測設備的發展，分析了各種設備的優劣，並在此基礎上提出了採用光電檢測技術對軌道不平順參數進行檢測的三套方案：光敏二極體陣列方式、線陣ccd結合工業控制計算機方式和線陣ccd結合單片機方式。 -
After the investigation of the general technology of hardware implementation, how to implement the kasumi algorithm using field programmable gate array ( fpga ) device is discussed in detail, and the author develops the cipher chip of kasumi algorithm, the kasumi cipher card based on 32 - bits pci bus, the wdm device driver that used in windows2000 / xp, and the software to demostrate encrypting data link. finally, an application demostration is constructed with all the above implementation
在此硬體實現的結果晶元基礎上，設計了32位的基於pci總線的kasumi加密卡，編寫了windows2000 xp下的windows驅動程序模型（ wdm ）驅動程序和鏈路加密應用程序，由此構成一個應用演示系統，作為研製結果的應用評估，為進一步進行第三代移動通信系統相關安全技術研究和開發提供了基礎條件。 -
In this paper, the method of digital evolvable hardware is studied based on the dynamical reconfiguration of field programmable gate array ( fpga ). in the paper, firstly, the basic conception and theory of ehw are roundly introduced and the structure characters of ehw chip are analyzed. secondly, the thought of standard evolutionary algorithm is discussed and the flow of improved evolutionary algorithms is analyzed
本文首先較全面地介紹了硬體演化技術的基本概念和原理，分析了演化硬體晶元的結構特點；其次，討論了標準演化演算法的思想並對改進型演化演算法的流程進行了分析；然後著重分析了演化硬體實現中的關鍵技術，對其實現方案進行了深入的研究，文中分別採用外部演化和內部演化兩種方式對不同的應用電路進行了演化。 -
The advent of dna micro - array make it possible to perform gene diagnosis and gene treatment. gene selection is one of the major challenge of gene - chip technology, for gene diagnosis where only a gene subset is enough for diagnosis of diseases, for resolution of curse of dimensionality which occurs especially in dna microarray dataset where there are more than thousands of genes and only a few number of experiments ( sample )
基因晶元的出現為基因診斷和基因治療提供了很好的前提和可能性，超高維空間超小樣本的基因選擇問題是基因晶元技術的挑戰性課題之一，對于解決維數發難問題和獲得診斷基因具有重要的理論和實際意義。 -
At last, through calculation we get the two dimensional temperature distribution of the chip and the submount of a high power laser diode array, which are consistent with the test data
最後，通過實驗測定激光器陣列有源區的溫升，得到與理論計算基本一致的實驗數據，並且對溫度的數值計算做了進一步的討論。 -
The method of design of system on chip ( soc ) based on the field program gate array ( fpga ) is also introduced
並對課題中採用的基於現場可編程門陣列（ fpga ）的片上系統（ soc ）設計方法進行了介紹。 -
And then, aiming at the deficiency of conventional design, the high - compositive fpga ( filed programmable gate array ) chip is used as the core in this project to deal with the signal of six encoders in real time
其次針對以往設計的不足，採用了以高度集成的fpga （現場可編程邏輯陣列）晶元為核心的設計方式，實現六路光電編碼器信號的同步實時處理。 -
This paper research the principle of two dimensional collimator system in which the area - array ccd, cpld circuit and dsp chip are used. digital acquisition and processing hardware and software were designed. the test result was given
本文研究了用cmos作為接收器件，用cpld電路和dsp晶元進行系統流程式控制制和數據處理的二維變形測角儀的系統原理，設計了數據採集、處理的硬體軟體，並進行了實驗。 -
Now if we suppose that the rated temperature limit of any chip were identical, confining the highest temperature in the rated limit is the most important, for this purpose i apply the principle of annealing algorithm to the optimization of place distribution design. under the unvaried condition of thermal dispersion, we can get the least temperature of the maximum value in some kind of chip array
為了使得電子元件最大溫度負荷在特定散熱狀態下達到最低（低於額定的最高溫度值） ，我們將模擬退火演算法的優化設計思想應用到電子元件陣列的布局優化中，使得在不改變外部散熱條件的情況下，僅僅通過電子元件位置分佈的改變就取得降低其最高工作溫度的效果。 -
The last effort in this paper is concentrated on the readout circuitry of microbolometer arrays, which is connected to the detector array on chip to form a monolithic chip, and the non - uniformity correction
這一模擬軟體對微測輻射熱計的設計研製具有指導意義。研究了微測輻射熱計陣列讀出電路並進行了非均勻性校正。 -
This paper goes on with analysis of the phased array radar calibration theory and compare of different schemes, then the best is adopted. 2 mhz digital circuit mainly composed of dds ( direct digital synthesis ) chip, which carries out the shift of the phase and the limit of the amplitude, has been designed and debugged successfully. it is used to substitute for the conventional phased shift circuit and amplitude limiting circuit which work at the radio frequency, so the all - digital transmit channel of phased shift array radar is achieved
本論文研究的重點是：針對傳統相控陣雷達系統收發（ t r ）組件中的移相和限幅功能均在射頻段完成，大膽利用直接數字合成（ dds ）晶元組成頻率在2mhz左右的數字電路代替傳統相控陣雷達在射頻段進行移相和限幅的電路，從而組成全數字發射通道，使對相位和幅度的控制和調試更方便快捷，並設計具體的電路驗證此方案的可行性。 -
For the high - speed digital signal processing, the structure of fpga and dsp is widespreadly adopted. dsp is more featured in the implementation of complicated algorithm, while field programming gate array ( fpga ) shows more advantage in its flexibility of design, simplicity of system configuration, modification and maintenance. in the paper, the hardware system of the spaceborne radar is based on the structure of fpga and dsp, of which the signal processing part is accomplished with one fpga chip and multi dsps
Dsp適合完成結構復雜的演算法;現場可編程邏輯陣列（ fpga ）適合完成高效、演算法固定的任務;與專用集成電路（ asic ）相比， fpga優點主要在於其很強的靈活性、可在線配置、修改和維護方便等優點。本文工程中的星載雷達信號處理和控制系統就是採用dsp + fpga的方式。其中信號處理採用的是xilinx公司的virtex -和virtex系列fpga和多片analogdevices公司的tigersharcts101的硬體電路結構。 -
A large array of products are built around highly modified powerpc 400 family cores, not the least of which is the blue gene supercomputer with two powerpc 440 processors and two fp floating point cores per chip
大量的產品都是在對powerpc 400系列的核心進行高度修改而構建的，其中「藍色基因」超級計算機就在每個晶元中採用了兩個powerpc 440處理器和兩個fp （浮點）核心。 -
Cmos process is used to realize the one chip integration of the sensor array and processing circuits, which accords with the development direction of soc ( system on a chip ) and smart sensor
傳感器使用標準cmos工藝製造，將傳感陣列與信號處理電路集成在同一晶元上，可以實現傳感器的soc集成和智能化（ smartsensor ）設計。 -
This paper researches the integrating application of adaptive antenna array technology, spread - spectrum communication technology and transform - domain filter technology in shortwave communication area, basing on the background of improving on the shortwave communication equipments being used in chinese army, and all the key techniques mentioned above are implemented in a single fpga chip
本文以改造我軍現役短波通信設備為背景，研究了自適應天線陣技術、擴頻通信技術、變換域濾波技術等多種現代數字信號處理技術在短波通信中的綜合應用，並以單片超大規模fpga晶元為硬體處理平臺，對系統中的關鍵技術進行了設計與實現。 -
This dissertation develops research work for some fields in which ground clutter suppression algorithm may be used for airborne phased - array radar, software design of 3dt - - stap algorithm with adaptive space - frequence steer vector algorithm is completed for clutter suppression realtime processing system based on tigersharc ts101 chip
本論文圍繞機載相控陣雷達的空時二維處理技術展開研究工作，主要任務是為系統選擇地雜波抑制的演算法，並完成以浮點dsp晶元（ ts101 ）為核心的基於3dt
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