buffer gate 中文意思是什麼
buffer gate
解釋
「或」門-
By comparing and analyzing the advantages and disadvantages of three kinds of voltage reference circuits, type of current density ratio compensation 、 weak inversion type and type of poly gate work function, a cascode structure of type of current density ratio compensation is chosen to form the core of voltage reference circuit designed in this paper. applying the negative feedback technology, an output buffer and multiply by - 2 - circuits are designed, which improve the current driving capability
然後通過比較和分析電流密度比補償型、弱反型工作型和多晶硅柵功函數差型三種帶隙電壓基準源電路結構的優缺點，確定了電流密度比補償型共源共柵結構作為本設計核心電路結構，運用負反饋技術設計了基準輸出緩沖電路、輸出電壓倍乘電路，改善了核心電路的帶負載能力和電流驅動能力。 -
Based on the analysis of the calculation method of traffic lane number for the gate of container terminal, present design criteria and existing problem of the length design for buffer parking area of terminal entrance, this paper studies the arrival characteristics of container trailer and puts forward a calculation method based on random service system ( queuing theory ), for calculating the optimum traffic lane number and length of buffer parking area for the gate of container term ma1, with an explanation of the calculation procedure by an example, to serve as a reference for similar projects
摘要通過分析集裝箱碼頭大門車道數的計算方法及其停車緩沖區長度的設計現狀、存在問題，根據集裝箱碼頭大門施掛車的到達特性，提出基於隨機服務系統（排隊論）的集裝箱碼頭大門最佳車道數及其停車緩沖區長度的計算方法，並通過示例說明該方法的計算過程，為類似工程提供參考。 -
An algorithm of path - based timing optimization by buffer insertion is presented. the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation. and heuristic method of buffer insertion is presented to reduce delay. the algorithm is tested by industral circuit case. experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied
提出了一種基於路徑的緩沖器插入時延優化演算法，演算法採用高階模型估計連線時延，用基於查表的非線性時延模型估計門延遲.在基於路徑的時延分析基礎上，提出了緩沖器插入的時延優化啟發式演算法.工業測試實例實驗表明，該演算法能夠有效地優化電路時延，滿足時延約束 -
The resonance network is connected to the gate, then the output and input matching network is designed to satisfy the oscillation criteria. then harmonic balance method is used to analysize and optimize the output power and phase noise. to minimize the load pulling effect a buffer amplifier is designed to isolate the oscillator and the load
本文在場效應管fet柵極上加上諧振網路（諧振網路是通過cst模擬得到的，它是串聯反饋迴路，介質工作在te01模，對于其後的fet ，它又相當於一個帶阻濾波器） ，然後設計輸入輸出匹配電路，使電路結構滿足起振條件，之後繼續用諧波平衡法模擬和優化，使振蕩器輸出功率合適，相位噪聲很低。 -
Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired
在超導rsfq數字電路模型的理論分析基礎上，論文中採用wrspice對超導rsfq數字電路進行時域模擬，得到了超導jtl傳輸線，緩沖器， rs觸發器， t觸發器，或門等基本邏輯單元電路以及電路參數。
分享友人