bus control logic 中文意思是什麼
bus control logic
解釋
總線控制邏輯-
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。 -
Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo
本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。 -
This software system of chip simulation ' s main function is simulate the main logic circue chips, 8088cpu, memory, registers, data _ bus, address _ bus, control _ bus and other chips. this function is based on the object - oriented technology, construct the chip object by the chip classes that we defined. because this system need to simulate the detail function of computer hardware, so this system simulate the 8088cpu ' s order system, support the basic compile languages. one of the feture of this system is the simulation of a static memory, the room of the memory can be configured by testers from 1k to 64k
由於本系統在模擬過程中需要完全模擬計算機硬體的工作原理，因此本系統還模擬了8088cpu的基本指令系統，支持基本的匯編指令，在實驗過程中可以由實驗者輸入相應的匯編指令以執行操作，並查看各晶元器件的引腳參數變化情況。本系統模擬的一個特點是動態模擬了存儲器的大小，存儲器容量可以由實驗者根據需要自己設置，范圍從1k到64k 。 -
Programmable logic design on pci9054 local bus control
9054本地總線控制可編程邏輯設計 -
Abstract : this article retrospects the development of sequence control system in thermal power plants at home and abroad ， especially introduces the three developmental stages of sequence control system in china over the past 35 years ， i. e. ： 1. starting stage ； 2. the second stage with programmable logic controller ( plc ) as core hardwares ； and 3. the third stage with sequence control systems of main and auxiliary equipment incorporated into the distributed control system ( dcs ) and with field bus control system ( fcs ) got involved. this article also appraises the features of sequence control system composed of different configurations and looks forward to the developmental tendency of this system for the next century
文摘:回顧國內、外火電廠順序控制系統的發展，特別介紹35a來我國順序控制系統經歷的起步階段、以程序控制器（ plc ）為核心硬體的中期階段和主、輔機順序控制系統融入分散控制系統（ dcs ）階段、現場總線控制系統（ fcs ）介入階段，並對由不同形式組成的順序控制系統的特點進行評價，展望下一世紀該系統的發展趨勢。 -
In the thesis, based on design and implementation of the two signal processing system of different requirement, multi - dsp processor structure, dsp - pci interface, system control logic, pci device driver program, user application program are researched. the main content is list as follows : 1 ) according to the lfmcw radar signal processing algorithm, a signal processing system based on pc104 - plus bus is developed
本文通過對以上兩種雷達信號處理機的設計開發過程，研究了採用多片dsp信號處理器組建并行處理模塊實現信號處理演算法的方法，利用pci總線實現處理機數據傳輸介面，設備驅動程序和控制界面軟體開發，實現信號處理機數據傳輸控制等幾個方面的內容，主要工作如下: 1 ）針對線性調頻連續波雷達信號處理演算法，完成了基於pc104 - plus總線的嵌入式信號處理板的設計、製作以及調試。 -
In data sampling circuit, high - speed, complex programmable logic device cpld technique is used. high - speed double - port ram, control sampling time sequence logic, cpu interfaces and bus circuit are implemented in cpld. sampling speed is up to 80mhz, sampling depth is ik - byte, and cpld can fulfill the requirement of the software arithmetic to sampling
在數據採集電路中採用了高速復雜可編程邏輯器件cpld技術，晶元內設計有高速雙埠ram 、控制采樣時序邏輯及cpu介面、總線等電路，采樣速率高達80mhz ，采樣深度1k位元組，很好地解決了超聲波微位移傳感器軟體演算法對采樣的要求，並可實現在線升級，大大提高了系統的整體性能。 -
A n lh control system structure, based on high speed ethernet, field bus, programmable logic controllers and general purpose pcs, is proposed. after analyses of the key control elements - temperature and composition, the thesis gives detailed design of the main system control functionalities : electrode control system, alloy material adding control system and operation monitoring system
在此基礎上，提出了基於工業高速以太網、現場總線、可編程邏輯控制器、通用工業pc的系統結構方案。分析了lf爐的關鍵要素? ?溫度控制和成份調節，對電極控制系統、合金加料系統及操作監控系統等主要控制系統功能進行了詳細設計。 -
The control logic is completed by fpga. the system control software provides several control functions of pci and dsp, such as adjusting pci bus configure registers, setting work mode, downloading dsp programs and data, reading processing results from dsp and saving data
系統控制軟體提供了pci和dsp的控制功能：修改pci總線的配置寄存器、設置工作方式、向各個dsp下載用戶程序與數據、從dsp中讀取處理結果、數據存檔等操作。 -
The digital upward frequency conversion is the key element of the waveform synthesis. at the same time, basic theoretical analysis and optimum design are done for pci bus slave interface, fifo, transmit signal processor, digital - to - analog converter and logic control
本文對波形合成技術的核心? ?數字上變頻進行了深入細致的研究和介紹，同時對波形合成器中的pci總線介面、先進先出緩沖器、發射信號處理、數模轉換及邏輯控制等部分進行了分析和優化設計，給出了最佳設計方案。 -
Design of logic control circuits, device driver and application of the high - speed data communication system based on pci bus are completed. with s5933 bus master ( dma ), bidirectional and high - speed data transmission are realized
本文完成了基於pci總線的雙機高速數據通信系統的邏輯控制電路設計、驅動程序及應用程序的開發，實現了s5933總線主控（ dma ）方式的雙向高速數據傳輸功能。 -
According to the necessity of cpci - gpib controller interface module, analyzing the cpci bus, gpib bus and interface function in detail, the design accomplished the function of bridging connection, conversion of protocol, logic control and so on
本文根據設計cpci - gpib控制器介面模塊的需要，在詳細分析cpci總線、 gpib總線協議及介面功能的基礎上，完成了設計任務，並實地驗證了cpci與gpib總線之間的橋接、協議轉換、邏輯控制等功能。 -
The peripheral equipment, which includes serial control, b3g test tools, ddr control, interrupt control, connect the on - chip peripheral bus of powerpc ~ ( tm ) 405. in addition, the clock module and the misc logic module are necessarily to make the b3g test platform work. in order to debug the b3g test platform, the chipscope ~ ( tm ) core is adopted
在powerpc ~ （ tm ） 405的外圍總線上開發了串口控制器、 b3g測試工具、雙倍數據流（ ddr ）內存控制器、中斷控制器等外設;整個系統還需要時鐘、輔助邏輯等模塊;為了方便b3g測試平臺的調試，將chipscope ~ （ tm ）核也嵌入到了平臺中。
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