chip size 中文意思是什麼

chip size 解釋
集成電路片尺寸
  • chip : n 1 碎片，削片，薄片；碎屑；薄木片；無價值的東西。2 （陶器等的）缺損（處）。3 （賭博用）籌碼；〈p...
  • size : n 1 大小，尺寸規模身材。2 （鞋帽等的）尺碼，號；（紙張的）開。3 巨大，大量；相當大的分量。4 〈口...
  1. It is pointed out that the image resolution is in proportion to the size of the ccd chip and in inverse proportion to the recording distance

    從理論上分析了產生這些誤差的原因，同時作了計算機模擬與數值分析。
  2. The card will look similar to a photocard driving license, which is similar in size to a credit card. also being considered is having the individual s fingerprint or iris image stored in the memory chip of the card to identify the cardholder and prevent any fake cards

    公民咭外型與含照片的駕駛執照相似，大小則近似信用咭。為了防止偽咭，咭內晶片會載有持咭人的指模或虹膜影像，此舉引來輿論關注。
  3. Increasing the window size and the issue width to extract more ilp may hinder from achieving high clock speed, limiting over - all performance, especially for the forthcoming billion - transistor per - chip era

    在這種情況下，再增加動態指令窗口的體積和發射寬度將無助於高主頻的實現，難以開發更高的ilp ，獲得整體性能的提升。
  4. Monolithic optoelectronic integrated circuits ( oeics ) integrate optoelectronic components and electronic components onto one chip. it has the advantages of high speed, small size and cost - effective. the fabrication of monolithic oeics is confronted with the incompatibility problem between optoelectronic components and electronic components

    單片光電集成器件（ oeics ）是利用光電子技術和微電子技術將光電子器件和微電子器件集成到同一襯底而形成的新型器件，具有功能強、體積小、成本低等突出優點。
  5. Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout

    本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。
  6. The cooling system for engine adopted hydraulic drive and control technology to control the speed of the fan : the chip adjust the control - current of the proportional value, which used in the engine cooling system, to control the speed of the fan. and the size of the control - current is according to the coolant temperature, coolant temperature change rate and target temperature. as for as the hydraulic cooling system we used a motor to drive and control the fan ’ s work or stop according to the temperature of the hydraulic oil

    該系統的特點及其實現的功能為:電液混合驅動方式改變了工程機械冷卻裝置驅動方式單一的缺點，發動機冷卻系統採用了電液比例技術控制風扇轉速;單片機可以根據冷卻液溫度、冷卻液溫度變化率和目標冷卻液溫度調節液壓驅動系統中電液比例閥的控制電流，進而控制液壓油的流量，即可以實現冷卻風扇轉速的連續調節;液壓油冷卻系統採用了電動機驅動，然後由單片機根據液壓油的溫度控制電動機的起動和停止。
  7. The type of packages and the methods in which it is possible to mount the finished semiconductor chip ( depending on factors such as heat dissipation, size, etc. )

    封裝的類型和方法（它們取決于熱耗散和尺寸大小等因素） ，用此種方式即可安置經過精製的半導體晶元。
  8. Ultrathin wafer level chip size package technology

    超薄型圓片級晶元尺寸封裝技術
  9. Jennic is unique in combining expertise in systems and software with world class rf and digital chip design, so our integrated circuit solutions for these wireless sensor networks lead the market in size, power, and cost

    2004重新定位，成為技術領先的無工廠半導體供應商。核心技術: rf與混合訊號設計，嵌入式系統及網路協定開發。超過四十人的技術團隊，超過五年的共同開發經驗。
  10. Chip size limits

    電路片尺寸限制
  11. On the design of the system, the thickness measure system of mems chip is built based on lbu and pump - probe technology. on the analysis of data, the reflectivity curve is analyzed using the law of reflectivity change induced by ultrasound, and the thickness is calculated using the system designed by the article, to aluminum film the size of about 20nm can be measured, when the film be measured is single layer, the relative error of the system is less than 2 %, when the film be measured is double layer, the relative error of the system is less than 10 %

    在基礎理論方面研究了激光（特別是超短脈沖激光）超聲的激勵機理，探討了激光調制技術以提高系統信噪比，闡述了泵束探針束技術及相關實驗設置；在系統設計上，以激光超聲為基本原理，以泵束探針束技術為系統設計方案完成了mems基片厚度測量系統的設計；在數據分析方法上，利用聲致光反射率變化的一般規律對測得的光反射率曲線進行分析，確定超聲回波在薄膜兩界面間來回傳播的時間，以計算薄膜的厚度。
  12. The technique core of the 3 - d outline tracking scan lies in the adoption of several photoelectric sensors, laser measuring sensors and super voice wave measuring sensors to carry on probing, the single chip makes the photoelectric signal examined as the control basis, and controls the step motor to drive measurement machines and probing sensors to make outline tracking and scans movement along high and breadth direction of the vehicle, and record its outline track, and the data measured is delivered to the computer, finally, acquires the size of the vehicle checked through the place of computer data processing

    三維輪廓跟蹤掃描技術的核心在於採用多套光電傳感器、激光測距傳感器、超聲波測距傳感器進行探測，單片機把檢測到的光電信號作為控制依據，控制步進電機驅動測量機及探測傳感器在車長、車高和車寬方向上作輪廓跟蹤掃描進給運動，記錄其輪廓軌跡，並把測得的數據傳送到上位機，經上位機數據處理獲得被檢車輛的特徵尺寸。
  13. To reduce the size and increase the reliability of the control card, lattice company ? isplsi chip is used to realize the digital logic circuit. its insystem programmable ability makes it easy to realize the design of digital logic circuit

    6軸伺服控制卡上，使用lattice公司的isplsi器件實現數字邏輯電路設計，降低了板卡的設計尺寸，增加了電路板的可靠性和設計靈活性。
  14. Today, we can put as many transistors as the total number of people on this earth onto a silicon chip the size of a thumbnail

    目前已經能在拇指指甲大小的硅晶片上超精密地製造出相當于全世界人口數目的晶體管。
  15. Standard eia chip size available

    標準eia貼片尺寸
  16. In terms of chip size, it s actually smaller than merced, and yet it s in the same process

    在晶元大小方面，它實際上比merced小，而採用的是同樣的加工工藝。
  17. Ut - scsp ultra - thin - stacked chip size package

    超薄疊層晶元尺寸封裝
  18. According to process rules of the gaas mmic product line, we properly designed the circuit layout. in order to reduce the overall chip size, the transmission lines are folded with sufficient spacing to avoid interline coupling. the lange couplers are also folded to keep the 90 and 180 bits " sizes similar to other phase shift bits " sizes

    結合實際mmic工藝線，合理設計移相器電路版圖，折疊微帶線並留出足夠大的線間距，以避免線間寄生耦合的發生，並折疊蘭格耦合器使90和180移相位的尺寸與其它相位的晶元尺寸保持一致。
  19. Similar with design verification problem, to predigest chip level layout synthesis problem, the layout synthesis based on the standard - cell methodology can be divided into two levels : inner standard - cell and among standard - cells. however, along with the increasing of chip size, chip level layout synthesis problem become more complex if it still bases on general manual standard - cell. because the router cannot impose the characteristic of the transistors in the standard - cell, it may reduce the performance of the whole chip

    通常，基於標準單元布圖模式將版圖綜合劃分成單元內與單元間兩個層次，以簡化晶元級自動版圖綜合問題的復雜性；但隨著晶元規模的不斷擴大，基於主要以手工定製的小規模標準單元，晶元級版圖綜合問題的復雜性不斷增大，且標準單元間布線無法充分利用單元內晶體管特徵，影響晶元的整體性能。
  20. This increase in chip size means that designs get more complicated because they must manipulate and hold larger systems called soc, or " system - on - chip ", designs

    晶元尺寸的增加意味著設計工作將變得更加復雜，因為他們必須操作、控制更大的系統（稱為soc或" system - on - chip "設計） 。
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