circuit description 中文意思是什麼

circuit description 解釋
電路說明
  • circuit : n 1 （某一范圍的）周邊一圈；巡迴，周遊；巡迴路線[區域]；迂路。2 巡迴審判（區）；巡迴律師會。3 【...
  • description : n. 1. 記述，敘述，描寫；記載。2. 敘事文；（物品）說明書；相貌說明書。3. 種類。4. 作圖；繪制。
  1. The essential aspect of the mathematic model for inductor is the description of the hysteresis loops of the magnetic core material. the jiles - atherton ferromagnetic theory combined with the experience formula proposed by h. g. brachtendorf, c. eck and r. laur, was applied in this case. the model is more flexible than jiles - atherton ’ s, especially in the circuit model convert

    本文採用了由h . g . brachtendorf 、 c . eck 、 r . laur提出的經驗公式與jiles - atherton鐵磁磁滯理論相結合的修改新數學模型，並將該模型轉換為等效電路模型模擬磁滯特性，實驗結果表明，該模型比jiles - atherton模型靈活，利於轉換為宏觀電路模型。
  2. Multi - rate circuit - mode bearer service for isdn - addendum to the circuit - mode bearer service category description

    Isdn多速率線路模式載體服務.線路模式載體服務類別描述的附錄
  3. After that, the hardware circuit, especially some of the key parts, is investigated in detail. the following processes are also investigated in detail : empoldering the four fold - frequency subdivision 、 direction - judgment 、 counting and flip - latch of the data with vhdl ( very high speed integrated circuit hardware description language ) ; empoldering the serial interface and the data collection software in pc with borland c + + builder

    接下來詳細介紹了使用vhdl語言開發fpga晶元的細分、辨向、計數、鎖存以及串列傳輸處理等全部功能;用borlandc + + builder開發了pc機上的串列介面、數據採集軟體;設計並製作了fpga晶元及其外圍電路的電路板。
  4. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  5. Integrated circuit computer hardware description language verilog

    集成電路計算機硬體描述語言verilog
  6. As a result, this design accomplishs the function of circuit, which not only can satisfy the high speed image data transmission of large screen system and improve the performance of circuit, but also increase the flexibility of circuit design. in the design, it is possible to act hardware description language procedure according to the practical application demand, instead of revising hardware design of the circuit, which reduce the design cycle and the cost

    所以，本課題運用可編程邏輯器件來完成電路功能，不僅能夠滿足大屏幕系統高速圖像數據傳輸對速度的要求，改善了電路性能，而且增加了電路設計的靈活性，設計中可以根據實際應用的需求靈活修改相應硬體描述語言程序，而不需要修改電路硬體設計，縮短了設計周期，降低了成本。
  7. The methods of adopting fpga to realize the function of counter, and adopting verilog hdl hardware description language to design every function modules, not only makes the whole design more compact and stable, but also make the alteration of the circuit ’ function merely need to alter the software according to the practical task requires, and needn ’ t alter the hardware connection of the circuit

    在計數器功能的實現上採用fpga （ fieldprogrammablegatearray ） ，利用veriloghdl （ hardwaredescriptionlanguage ）語言編寫了各個功能模塊，不僅使整個設計更加緊湊、穩定且可靠，而且可以根據實際的任務要求，在無需改變硬體電路板的情況下，通過修改硬體描述語言程序，即可修改電路功能。
  8. As a research trial for this thesis, we designed a real circuit based on cpld ( complex programmable logic device ) by vhdl ( very high speed integrated circuit hardware description l anguage ) for the hardware algorithm for euclidean distance transform with multilayer design method, called top - to - down

    一down ）的方法，設計了一個基於復雜可編程邏輯器件cpld （ co哪lexprogammablelogiedeviee ）的基本電路，用以驗證基於硬體的歐幾里德距離轉換演算法的各項性能。
  9. According to the hardware structure of the main experiment board, the circuit netlist transformation program translates the visual circuit description to the actual netlist

    根據實驗主板的硬體結構，設計的專用電路網表轉化程序，將便於用戶理解的圖形化的電路描述轉化為便於實際硬體操作的電路網表。
  10. Description : this neurophone incorporates an electronic circuit duplicating the encoding of the cochlea and 8th cranial nerve themselves

    描述：這個腦聽器包含了一個電子電路復制他們自己的耳蝸的編碼，第8腦神經。
  11. Explicit description of main circuit topology, operation principle, characteristic of the circuit of the novel phase - shifted zero - voltage and zero - current switching pwm dc / dc full - bridge converter as well as the simulation analysis with the pspice software is proposed

    對移相控制zvzcs下pwm的dc dc全橋變換器的拓撲結構、工作原理和電路特性作了深入的闡述，採用pspice軟體進行了計算機的模擬分析。
  12. This dissertation is supported by the following projects : national foundation for science research on the theory of sub - deep micro and super high speed multimedia chip design " ( no. 6987601 0 ) national foundation for high technology research & development " interface of vlsi ip core and related design technology " ( 863 - soc - y - 3 - 1 ) a - national r & d programs for key technologies for the 9th five - year plan research on high level language description and embedded technology for mcu " ( 97 - 758 - 01 - 53 - 08 ) national foundation for the ministry of education, prc " research on the optimal theory and methodology of soc software / hardware integration co - design and co - verification " ( moe [ 2001 ] 215 ) national foundation for science and technology publication " design of interface circuit for computer with verilog " [ ( 99 ) - f - l - 011 ] a deep research on system level design methodology of 1c and the design technology of mcu - ip and interface ip are made in this dissertation. the main work and achievements are as follows : 1 building block principle and the building block component maximum principle are brought forward based on the research of developing history of ic design

    本文基於以下科研項目撰寫：國家自然科學基金「深亞微米超高速多媒體晶元設計理論的研究」 （ 69876010 ）國家863計劃「超大規模集成電路ip核介面及相關設計技術」 （ 863 - soc - y - 3 - 1 ）國家「九五」重點科技攻關「 mcu高層語言描述及其嵌入技術研究」 （ 97 - 758 - 01 - 53 - 08 ）國家教育部「 soc軟硬體集成協同設計和驗證優化理論和方法研究」 （教技司[ 2001 ] 215 ）國家科技學術著作出版基金「 verilog與pc機介面電路設計」 （ 99 - f - 1 - 011 ）論文的主要工作和取得的成果如下： 1 、在研究集成電路設計方法學發展歷史的基礎上，提出了設計的積木化原則和積木元件最大化原則。
  13. Vhdl : very high speed integrated circuit hardware description language

    超高速集成電路硬體描述語言
  14. And the controller based on vhdl ( very high speed integration circuit hardware description language ) was designed under the fpga ( field programmable gates array ) integration environment with the values gained from the train of the neural network using matlab

    氣動柔性手指神經網路控制器是在已經對氣動柔性手指進行運動學和動力學分析的前提下，使用matlab對神經網路進行試訓，依據訓練所得的權值和閾值，在現場可編程門陣列集成環境下，基於超高速集成電路硬體描述語言完成的。
  15. In order to make the speed of the function simulation faster, the system adopting vhdl ( very high - speed integrated circuit hardware description language ) to make simulation faster, at the same time this make it easy to transplant the circuit to other kinds of isp chips

    為了提高模擬的速度，對部分電路採用vhdl語言進行邏輯描述。通過實驗證明，在微波測距儀中採用在系統可編程邏輯器件，收到了很好的效果。
  16. The paper analyses the features of mmc2107 in detail, designs circuit diagram of the software debug platform, presents an accurate description of the logic symbol in complex programmable logic device, gives a detailed discussion about the operating mechanism of target resident kernel and the customization of the system software

    文中詳細地分析了mmc2107的功能特性，設計了軟體調試平臺硬體電路，給出了復雜可編程邏輯器件的內部邏輯圖，論述了駐留程序的工作機制並定置了系統程序。
  17. The hardware circuit boards are produced by a laser photoplotter according to the gerber files gererated from the schematic ( sch ) documents and the printed circuit board ( pcb ) documents. the cplds, programmed with the verilog hardware description language ( verilog hdl ), were completed after four steps : design, simulation, synthesis and fit. the software is developed with c language using direct i / o to communicate with the device through the isa bus computer interface

    其硬體電路由專業軟體設計出原理圖sch和印刷電路圖pcb生成，再gerber文件，然後光繪而成， cpld晶元編程（採用硬體描述語言veriloghdl ）經過設計、模擬、裝配、下載完成，高級軟體編程採用c語言i / o方式利用isa總線介面與外設進行通信。
  18. At the end of the thesis, the review on the developments of low - frequency square wave electronic ballast is given. then a novel two - stage low - frequency square wave electronic ballast for hid lamps is proposed with detailed proposed circuit analysis and control circuit description. finally simulation and experimental results are provided to verify its superiority

    論文最後對低頻方波電路的發展概況作了綜述，在此基礎上提出了一種新型的兩級式低頻方波電子鎮流器，並對其工作原理及控制電路進行了詳細的分析，最後通過模擬和實驗結果對電路進行了驗證。
  19. This paper has used the hardware language vhdl ( vhsic hardware description language ) to program some special circuit and prepared some work for the system on chip ( soc )

    利用硬體描述語言將調速控制所需的一些電路綜合在fpga晶元上為電機控制器向片內系統（ soc ）方向發展做了一定的工作。
  20. In view of numerous digital and analog signals need to be processed, and the difficulty of real - time processing of multi channel 400 hz ac signal, vhdl ( vhsic hardware description language ) is applied to design the digital circuit, which is successfully realized in field programmable gates array ic - xc2s100

    針對i o模塊中需要處理的數字量和模擬量較多的事實，以及多路400hz信號的實時處理較為繁重的現狀，作者採用了現場可編程門陣列（ fpga ）加以解決。
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