clock bit 中文意思是什麼

clock bit 解釋
時鐘位
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  • bit : n 1 少許，一點兒，一些；（食物的）一口，少量食物。 〈pl 〉 吃剩的食物；小片。2 〈口語〉一會兒，一...
  1. Each bit can flip 1020 times per second, equivalent to a clock speed of 100 giga - gigahertz

    每個位元每秒可翻轉1020次，大約比振?頻率10億赫茲的時鐘快1000億倍。
  2. The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox

    本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。
  3. Seven - o clock blowers a bit sin. i suppose i must

    「是的，我想我得起來了。 」
  4. Detail specification for electronic component. semiconductor integrated circuit. type ch2021 4 - bit up down synchronous binary counter dual clock

    電子元器件詳細規范.半導體集成電路ch2021型4位二進制同步加減計數器
  5. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  6. The current models have phased out the g3 but continue to use the similar g4, both 32 - bit chips, running at various clock speeds ; the recently introduced g5 is a 64 - bit ibm chip that mostly adds some multimedia - specialized instructions to the power4 chip models

    當前的g3型已經逐步被淘汰，取而代之的是類似的g4型，它們都是32位晶元，運行於不同的時鐘脈沖速度下；最近推出的g5是一款64位ibm晶元，主要是向power4型晶元中添加了一些多媒體專用指令。
  7. Fist, quick bit synchronization. the common methods are relative synchronization, multi - phase clock sample and so on

    第一，快速比特同步。常規的方案有相關同步法和多相位時鐘采樣法等。
  8. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。
  9. A 16 - bit risc microprocessor soft core is designed, and the instruction system, controller, bus and clock are studied

    本文設計了一個16位精簡指令集微處理器軟核16rmpu ，主要研究微處理器的指令系統、控制器、總線和時鐘等設計。
  10. Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains. the data transaction protocol comes from the most basic work way of uart. when the master clock is 16. 7mhz, the pcm side and adpcm side clocks both are 2. 38mhz, the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14. 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14. 7 us

    在主時鐘為16 . 7mhz ， pcm數據端與adpcm數據端時鐘均為2 . 38mhz時，模擬結果表明從pcm的起始位輸入uart接收器到adpcm終止位輸出uart發送器的最大延遲為14 . 3 s ，從adpcm的起始位輸入uart的接收器到pcm終止位輸出uart發送器的最大延遲為14 . 7 s ，設計時盡可能的使編碼與解碼的時間相差不多，從結果看出基本達到這個要求。
  11. According to elaborate analysis of clock logic in general purpose processor, we apply multi - bit clock gated flip - flops design to reduce the power of registers and clock trees concurrently, so the power of the clock network in processors can be drastically reduced. 3. a low power issue queue architecture is proposed

    一方面利用帶門控使能的觸發器電路降低時鐘節點的平均翻轉，另一方面通過多比特觸發器的採用進一步降低了時鐘樹規模，從而在不增加asic物理設計復雜度的情況下大大降低了龍芯處理器的時鐘網路功耗; 3 .提出了亂序多發射隊列的低功耗結構。
  12. The samsung s3c44box cpu is 32 / 16 bit risc microprocessor and uses arm7tdmi core. its maximum cpu clock frequency is 75mhz. the s3c44box is used in fields of cheap price handle devices and industry applications

    Samsungs3c44box是32 / 16位risc微處理器，它使用arm7tdmi內核，最高頻率可達75mhz ，主要用於廉價手持設備和一般工業應用領域。
  13. Slowing the cpu clock speed not only saves a bit of power but it also helps keep the cpu running cooler

    降低cpu時鐘速度不僅節省少許資源，而且它還有助於使cpu運行溫度更低。
  14. Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment

    Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。
  15. An idea is brought forth to design the total structure of the usb interface ip, the main control logic, the mcu interface ( the function is the same as the pdiusbd12 chip of the philips semiconductor ) and a dpll which is used to synchronize data and separate the clock. this paper also introduces packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding,

    提出設計了usb介面電路的整體構架，設計了usb的主要控制邏輯和與mcu的互連的介面（此介面與飛利普的usb介面晶元pdiusbd12兼容） ，也設計了一個數字鎖相環（ dpll ）來同步數據和分離時鐘，並對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。
  16. At the same time, this paper presents packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, clock / data separation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding, serial - parallel / parallel - serial conversion

    對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。
  17. Although ranging is adopted, certain phase shifts still exist between bit flows from onus to olts. therefore, fast synchronization must be applied to synchronize the receiving clock of olt to the bit flow being received from a certain onu

    雖然採用了測距技術，但是各onu到達olt處的比特流仍存在一定的相位漂移，所以必須採取快速同步的技術，將olt的接收時鐘同步到當前所接收的、來自某一onu的比特流。
  18. The effects of sampling clock jitter on signal - to - noise ratio ( snr ) and effective bit ( enob ) performance discussed in section 3 are even more dramatic in undersampling applications because of the higher input signal frequencies

    在第三章討論的采樣時鐘抖動對信噪比和有效位性能的影響在欠采樣應用中因為更高的輸入信號頻率顯得更有戲劇性。
  19. The dsp core of the dm642 is 32 - bit fixed - point dsps of c64x, with the performance of up to 4800 million instructions per second ( mips ) at a clock rate of 600mhz

    支持兩路ntsc / pal制式的視頻採集、處理和播放，設計了系統內部數據結構，對視頻幀圖像進行多格式軟體降采樣處理和運動檢測處理。
  20. Every pixel generates a bit data after front half of the clock cycle, then the pixel array generate a bit plane which is stored in sam

    每半個時鐘周期結束后每個像素就會產生一位數據，整個像素組就產生了一個位平面（ bitplane ） ，存儲在sam中。
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