clock buffer 中文意思是什麼
clock buffer
解釋
節拍緩沖器-
In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail
文章根據相關標準提出並實現了一種電路模擬專用晶元的設計方案，並對其中主要功能模塊和關鍵演算法作出了詳細說明，包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。 -
With vc - 12 virtual concatenation, we can make efficient and flexible use of the bandwidth. sdram, as a mass storage medium, is applied also. in this design, i use hy57v643220ct - 6, with 32bit data width, up to 166m system clock, as the buffer of vc - 12 virtual concatenation alignment and ethernet data transmission
本論文設計系統中採用了現代的hy57v643220ct - 6作為外部存儲器，它的數據線是32位寬，保證了吞吐量，時鐘可高達166m ，保證了速度，用它實現了多個以太網發送端緩存和多路vc - 12虛級聯的對齊。 -
Due to the concern of process variation, the delay of each clock buffer is treated as a range instead of a single value
在製程變異上面，每個時鐘緩沖器的延遲值被表示為一個范圍值。 -
Especially it allows various types of interruptions of external digital input, timer output and a / d conversion, each type of interruption has its own role in the signal measurement or in exact pace control, its fifo buffer function makes it possible to work at the sampling rate of 200k samples per second without carrying over - burden interruption rate, its latch type external interrupt request along with its high frequency clock makes a precise locating of pulse edges possible
該控制系統在工作過程中，有多種產生於不同部件的信號需要檢測，其中有模擬輸入信號十三路，數字輸入信號三路，通過數據採集和信號分析，判斷該控制系統工作是否正常。結合系統檢測的具體要求，本論文從硬體設計和軟體設計兩個方面，實現了數據採集系統的硬體介面電路和軟體演算法。
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