clock comparator 中文意思是什麼

clock comparator 解釋
時標比較器
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  • comparator : n. 【機械工程】比測器，比較儀，比長儀；【化學】比色計；比…器；【無線電】比較器；比較電路。
  1. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  2. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。
  3. The adm system mainly includes a oscillator, a clock generator, an amplifier, a pre - amplif ier, a comparator, an agc ( automatic gain control ), an adm analyzer & synthesizer, a d / a converter and a lowpass filter

    整個系統包括：內置振蕩器，時鐘產生器，放大器，前置運算放大器，比較器， agc （自動增益控制器） ， adm分析綜合器，數模轉換器以及低通濾波器。
  4. To cancel the offset - voltage of the comparator, a switch capacitance circuit is used between the three pre - amplifier stages. the charge pump circuit is used to boost the clock voltage of the switch transistor

    採用電荷泵電路提供開關管柵過驅動電壓，帶隙基準電路作為電荷泵穩定電壓的輸入，有利於改善開關電路的性能。
  5. And the ways to optimize the circuit architecture, minimize the circuit nonidealities and improve the circuit performance are analyzed combined with the characteristics of the modulator architecture. based on it, the switched - capacitor integrator, class a amplifier, nonoverlap clock, voltage reference, comparator, feedback dac have been designed. in the end, the layout design is shown

    調制器採用全差分開關電容電路實現，並根據系統結構特點就如何優化電路結構、克服電路中存在的非理想特性、提高電路性能作了具體分析，在此基礎上完成了開關電容積分器（開關、電容、運算放大器） 、參考電壓源、比較器、兩相非交疊時鐘、反饋dac等模塊的電路結構和參數設計。
  6. By careful selection of the ratio between this resistor and the integrating resistor ( a few tens of ohms in the recommended circuit ), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. 3

    通過小心選擇這個電阻和積分電阻之間的比值（在推薦線路里，大約是數十歐姆） ，比較器的延遲就可能被補償，最大的時鐘頻率可近似延伸到3 . 3倍。
  7. In order to make full behavior simulation of sigma - delta modulator, the noise models have been set, taking into account most of the sigma - delta modulator ’ s non - idealities and the final result supports the noise models. last, the main circuits of modulator have been designed, such as operational amplifier, comparator and clock generator, the design principle of noise - killed logic circuit has been presented. these circuits have been simulated

    調制器的噪聲模型，考慮了影響調制器性能的一些主要非理想因素，通過模擬驗證了噪聲模型的正確性;最後，設計實現了結構中的主要電路，如運放、比較器、時鐘產生電路，闡述了噪聲抵消邏輯電路的工作原理，利用hspice和cadencespectre對各電路進行了模擬，驗證其功能。
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