clock control signal 中文意思是什麼
clock control signal
解釋
時鐘控制信號-
The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。 -
This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution
主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。 -
The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions
本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。 -
And a kind of 16 - step automatic selective programmable amplifying circuit is designed in volume resistivity measuring circuit, so as to handle sampling little and broad signal. the control and disposal system with the core of microchip at89c55wd is analyzed on chapter 4. main function unit such as the interface circuit of lcd display and keyboard, the interface circuit of micro - printer, real time clock ds12c887, and hardware anti - jamming technique are discussed
本文還設計了以at89c55wd單片機為核心的控制處理系統的外圍介面電路及其軟體，對主要功能部分進行了分析，主要包括：鍵盤液晶顯示介面及界面設計、微型印表機介面、實時日歷時鐘晶元ds12c887 、單片機與單片機及單片機與上位機的通信設計以及控制系統硬體抗干擾措施等。 -
Clock control signal
時鐘控制信號 -
An improved high - resolution current - mode sorter is presented. its structure complexity is o ( n ), which is crucial to the expansion of its size, and its dynamic range is large. only one clock signal and one reset signal are needed. no biasing signal is required. the operation point is constructed according to the input current, so it is self - adaptive, which is very important for an all - purpose component. in average value circuit, subtraction circuit, winner - take - all ( wta ) circuit and control circuit, it has good performance even at a large input current. this sorter has high precision, high resolution and low power, as has been proved via hspice simulation. it can be implemented in the standard digital cmos technology and widely used in many fields, so it is of great value in applications
提出了一種改進的高精度電流型排序電路.它的結構復雜性僅為o （ n ） ，便於擴展;動態范圍大;它是自適應的，工作點由輸入電流確定，故不需要偏置信號，這對作為通用器件使用的排序電路來說是很重要的.通過利用平均值電路、減法電路、 wta電路和控制電路，可以使該電路在大輸入電流下依然保持高性能. hspice模擬表明該電路具有高準確性、高精度、低功耗的特點.它能用標準數字cmos工藝來實現，可以被應用於很多領域，具有很高的應用價值 -
Again, the keyboard / mouse always generates the clock signal, but the host always has ultimate control over communication
重復一遍，鍵盤/鼠標總是生成時鐘信號，而主機控制著整個通信過程。 -
The run stm program includes the control of scanning signal, supervise and control the running state, set the scan range, set parameters, set and acquire the clock, collect and save the image signal, etc. image manipulation functions includes : on the space of the wipe of speckle, smooth image, blur, step sharp image, laplace sharp, and automatically adjust contrast, etc
Stm運行程序包括掃描信號控制、運行狀態監控、設置運行參數，設置並獲得時基、圖像信號採集存取等等。圖像處理功能包括在空間域上的去斑、圖像平滑、模糊、圖像的梯度銳化、拉譜拉斯銳化，對比度自動調整等等功能，在頻域空間上完成數字圖像的傅立葉變換，並討論了理想高低通濾波。 -
An idea is brought forth to design the total structure of the usb interface ip, the main control logic, the mcu interface ( the function is the same as the pdiusbd12 chip of the philips semiconductor ) and a dpll which is used to synchronize data and separate the clock. this paper also introduces packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding,
提出設計了usb介面電路的整體構架，設計了usb的主要控制邏輯和與mcu的互連的介面（此介面與飛利普的usb介面晶元pdiusbd12兼容） ，也設計了一個數字鎖相環（ dpll ）來同步數據和分離時鐘，並對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。 -
At the base of earnestly analysis to the ov7620 working sequence, using its frame synchronization, field synchronization and the pixel - clock signal, completed gathering of the active power meter reading image which is reduced resolutions at the control of mcu
在仔細分析ov7620工作時序的基礎上，利用其幀同步、場同步和像素時鐘信號，在單片機的控制下完成了對電度表讀數圖像的降低解析度採集。 -
Especially it allows various types of interruptions of external digital input, timer output and a / d conversion, each type of interruption has its own role in the signal measurement or in exact pace control, its fifo buffer function makes it possible to work at the sampling rate of 200k samples per second without carrying over - burden interruption rate, its latch type external interrupt request along with its high frequency clock makes a precise locating of pulse edges possible
該控制系統在工作過程中，有多種產生於不同部件的信號需要檢測，其中有模擬輸入信號十三路，數字輸入信號三路，通過數據採集和信號分析，判斷該控制系統工作是否正常。結合系統檢測的具體要求，本論文從硬體設計和軟體設計兩個方面，實現了數據採集系統的硬體介面電路和軟體演算法。 -
The clock and data pulsation signals from upper sensor heads can be received using pin diode, then, amplified and inverted in logical control unit for the purpose of cpu operation. hereinafter, the digital signal will be delivered into the central processing unit ( cpu ) for related calculation, and meanwhile transmitted to a d / a converter for signal recovery after filter and phase - shift circuit
通過採用pin管接收從傳感頭傳遞下來的時鐘脈沖和數據脈沖信號，並將它們放大整形傳送到邏輯控制單元，產生邏輯控制信號，再將數字信號傳送給d / a轉換器，設計了濾波器和移相器電路，還原出了原始的被采樣信號。
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