clock recovery 中文意思是什麼

clock recovery 解釋
時鐘恢復
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  • recovery : n. 1. 重獲；復得；恢復，收回，回收。2. 還原，復原；痊癒；蘇生；矯正。3. 回縮。4. 填地。5. 【法律】勝訴。
  1. Clock recovery, cdr

    時脈恢復電路
  2. In this paper, a clock recovery system that based on phase control technology is studied

    本文設計的鎖相環路是基於相位控制技術的時鐘恢復系統。
  3. The clock recovery system is fabricated in tsmc 0. 25um cmos process. simulation in smartspice shows that the circuit as expected

    設計中採用tsmc0 . 25umcmos工藝，用smartspice進行設計模擬和優化。
  4. In the last part of this paper, simulation is given to show the performances of the clock recovery methods. the results prove the good jitter performances of the methods

    從模擬結果可以看出，同步時鐘統計恢復法具有很好的抖動性能，可以作為gpon系統tdm接入的一種高效時鐘恢復方案。
  5. Clock recovery is an important and difficult part of tdm access, so the thesis will emphasize on it. and two methods of clock recovery are proposed in the thesis

    然後，本文對同步時鐘統計恢復法進行了分析，推導出了時鐘信號低頻抖動的時域和頻域特性公式，並利用matlab對低頻特性進行了模擬分析。
  6. Gpon is multi - point to point network topology structure in upstream direction. in order to transmit tdm services, besides the common modules such as dba, fec, aes, the system also need data adjustment, clock recovery, and so on

    其中同步時鐘恢復是實現tdm接入的重點和難點，因此本文重點討論了同步時鐘恢復的方法，在研究atm和sdh時鐘恢復方法的基礎上，提出了同步殘余時標法和同步時鐘統計恢復法。
  7. In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail

    文章根據相關標準提出並實現了一種電路模擬專用晶元的設計方案，並對其中主要功能模塊和關鍵演算法作出了詳細說明，包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。
  8. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  9. A workforce of 250 is deployed to undertake the daily operation and maintenance of the tunnel and highway on a round - the - clock basis, including traffic control and management, vehicle recovery, traffic law enforcement as well as electrical and mechanical and civil works maintenance

    本公司擁有250名員工， 24小時不停地運作，負責隧道和公路的日常運作和維修，包括執行和管制交通法例緊急拖車服務及維修隧道內的電子機械及土木工程設施。
  10. If no measures are taken, the serious basic - line - shift as well as the loss of chip clock and the difficulty of the data recovery will be introduced in the optical receiver, which causes the communication to go along abnormally

    如果不採取任何措施，會給光接收機帶來嚴重的基線漂移，同時會引起碼時鐘丟失和碼元恢復困難等一系列問題，導致通信無法正常進行。
  11. The clock and data pulsation signals from upper sensor heads can be received using pin diode, then, amplified and inverted in logical control unit for the purpose of cpu operation. hereinafter, the digital signal will be delivered into the central processing unit ( cpu ) for related calculation, and meanwhile transmitted to a d / a converter for signal recovery after filter and phase - shift circuit

    通過採用pin管接收從傳感頭傳遞下來的時鐘脈沖和數據脈沖信號，並將它們放大整形傳送到邏輯控制單元，產生邏輯控制信號，再將數字信號傳送給d / a轉換器，設計了濾波器和移相器電路，還原出了原始的被采樣信號。
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