clock reference 中文意思是什麼

clock reference 解釋
時鐘參考
  • clock : n 1 鐘；掛鐘，座鐘，上下班計時計。2 〈俚語〉記秒錶，卡馬表；〈美俚〉〈pl 〉駕駛儀表，速度表，里程...
  • reference : n 1 （對委員、審查人等的）委託；委託項目[范圍]。2 說到，論到，提到。3 參考；參考書；附註，引證；...
  1. The method of observation resembles the stopwatch reference to a clock.

    觀測方法跟停表時鐘法相似。
  2. Reveals the objective necessity of the sole existence of absolute reference system 0 : the effect of clock losing and ruler contracting of any material system in motion with respect to 0 is the objective real physical change ( the real effect ) of this material system in motion, and the physical time and space ( the effect of motion ) is the unity of opposites between the external form of relativity correctly described by the special theory of relativity and the absolute internal essence with the objective sole existence of 0 as the basic marking, points out the errors of the general theory of relativity from the results above and the basic facts of gravitational field, and expounds the gravitational field is a real - time hollow field of motion in essence, and the physical time and space is the unity of opposites between mutually perpendicular images of void and real time and space of 4 dimensions each, understanding the absolute essence of the lorenz effect or not is the demarcation line between new and old views of time and space, and sets forth the theoretical gist of the time and space views of unity of opposites and the internal unity among the macroscopic level and straight time and space, the bent time and space in gravitational field, and the superimposed time and space in guantum state

    揭示了絕對參照系0唯一存在的客觀必然性：任何物系相對於0的「運動鐘慢、尺縮效應」 ，都是該運動物系客觀上具有蹬真正的物理變化（ 「真實效應」 ） ；進而揭示了物理時空（運動效應）是具有狹義相對論所正確描述了的相對性外部形式和以0客觀上唯一存在為基本標志的絕對性內在本質的對立統一運用上述結果和引力場的基本事實，論證了廣義相對論的錯誤；闡明了引力場本質上是一種實時虛空運動場；揭示了物理時空是互為正交映象的虛實各四維時空的對立統一闡明了對洛侖茲效應絕對性本質的認識與否，是新舊時空觀的分水嶺；闡明了對立統一時空觀的理論梗要和宏觀平直時空、引力場彎曲時空與量子態卷迭時空之間的內在統一性
  3. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  4. Timebase stability and clock reference

    時基穩定性和時鐘基準
  5. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。
  6. Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive - applied technique

    固定頻率源可以在在通訊系統和雷達系統中作為本機振蕩器，也可以作為數字電路的基準時鐘信號，因此得到了廣泛的應用。
  7. Clock reference board cki

    時鐘基準板
  8. And the ways to optimize the circuit architecture, minimize the circuit nonidealities and improve the circuit performance are analyzed combined with the characteristics of the modulator architecture. based on it, the switched - capacitor integrator, class a amplifier, nonoverlap clock, voltage reference, comparator, feedback dac have been designed. in the end, the layout design is shown

    調制器採用全差分開關電容電路實現，並根據系統結構特點就如何優化電路結構、克服電路中存在的非理想特性、提高電路性能作了具體分析，在此基礎上完成了開關電容積分器（開關、電容、運算放大器） 、參考電壓源、比較器、兩相非交疊時鐘、反饋dac等模塊的電路結構和參數設計。
  9. In its digital processing circuit, clock chip with high precision and temperature compensation is uesd as reference clock. high frequency reversible counter is used to count trimmed impulse signal forward or backward and two pathes saw signals are selected timely by multichannel selector

    數字信號處理電路採用高精度、具有溫度補償的時鐘晶元作為基準時鐘，採用高頻可逆計數器對整形后的脈沖信號進行正向或逆向計數，採用高性能的多路選擇器控制兩路saw信號的定時選擇。
  10. The 33220a external frequency reference lets you synchronize to an external 10 mhz clock, to another 33220a, or to an agilent 33250a. phase adjustments can be made from the front panel or via a computer

    33220a外部頻率基準使您能同步于外部10mhz時鐘另一臺33220a ，或agilent33250a .相位調整可從前面板或通過
  11. Chapter 2 describes the system part of mpeg - 2 standard with focuses on psi ( program specific information ) and pcr ( program clock reference )

    第二章主要講述了mpeg - 2標準系統層規范，著重介紹節目特殊信息psi和節目時鐘參考pcr 。
  12. In the same time, it is needed to revise pcr ( program clock reference ) in ts for the rate of ts is changed

    同時傳輸流的碼率發生了改變，需要對傳輸流的pcr作相應的修改，以消除碼率改變造成接收端機頂盒的圖像抖動。
  13. This thesis will give you a brief introduction on mpeg2 system layer, and then go on with the implementation of de - multiplex and multiplex in the transrating system, including processing specific program information and program clock reference

    本文將對mpeg2系統層進行簡單介紹，然後具體說明本課題系統層復用解復用過程的實現方法，包括比較關鍵的對節目特定信息的處理以及對系統時鐘的處理方法等。
  14. The minimum clock frequency is established by leakage on the auto - zero and reference caps

    最小的時鐘頻率，由自動歸零和基準電容的泄漏值確定。
  15. External clock reference input output lets you synchronize to an external 10 mhz clock, to another 33250a, or to an

    外時鐘基準輸入輸出使您能與外部10mhz時鐘另一臺33250a或agilent33120a同步
  16. Second, this dissertation implements separately a mpeg - 2 video decoder and a dolby ac - 3 digital audio decoder based on software mode, and gives a audio & video synchronization algorithm based on audio - clock - benchmark in mpeg - 2 system decoder, whose feasibility and practicability have been proved by experimenting. it is an all - purpose algorithm, which can perform different decoder according to mpeg - 1 or mpeg - 2 system models, and can also be used for reference to the implementation of other multiplex stream decoders

    然後，論文實現了基於軟體方式的mpeg - 2標準視頻及ac - 3格式壓縮音頻的實時解碼與回放，並依據mpeg - 2系統解碼模型實現了一種基於音頻基準時鐘的mpeg解碼器的視音頻同步演算法，實驗證明該演算法可行、實用、通用性好，對符合mpeg - 1或mpeg - 2系統標準的視音頻解碼器均具適用性。
  17. Primary reference clock pr

    主基準時鐘
  18. A utility to synchronize your system time with a reference clock is also provided. and you can uninstall your software

    還具有讓系統時間和世界上的原子時鐘同步，軟體的反安裝等功能。
  19. A new circuit of fan - out of high frequency clock was designed to provide a reference clock for the front electrical mode of pet system in the fourth " part of the thesis

    論文的第四部分介紹了為pet系統前端電子學模塊提供時間基準而設計的一種新型高頻時鐘扇出電路。
  20. In the multi - module mode both trig signal and reference clock are used for synchronization. the functional module supports dma with the dsp, which frees the dsp ' s core processor and entitles the real - time digital signal processing

    在數據傳輸方面無論是通過外部總線介面還是數據鏈路介面，功能模塊與dsp之間都支持dma方式，解放了母板處理器的核心運算單元，使實時信號處理成為可能。
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