coding circuit 中文意思是什麼
coding circuit
解釋
編碼電路-
To extent the use of this 1c, some circuit blocks are added. in the design, digital circuits are used to process the signal and control the precision of coding. and some circuits are used in different time by several functions to reduce the number of transistors used and the dissipation
電路設計中，為了便於信號處理以及控制編碼精度，採用數字的方法進行量階和預測碼的計算；同時，為了減小電路規模，採用了時分復用的概念，用同一部分數字電路實現量階調整和預測碼的生成，增加了編碼精度，減小了電路的規模和功耗。 -
The inversionless bm algorithm in rs decoder is implemented with serial mode, which avoids the inversion computation and only needs 3 finite - field multipliers. thus, the complexity of hardware implementation has been mostly reduced. a 3 - level pipe - line processing architecture is also used in the hardware and the coding circuit in rs coder is optimized by using the characteristics of the finite - field constant multiplier
Rs解碼器的設計採用無逆bm演算法，並利用串列方式來實現，不僅避免了求逆運算，而且只需用3個有限域乘法器就可以實現，大大的降低了硬體實現的復雜度，並且因為在硬體實現上，採用了3級流水線（ pipe - line ）的處理結構。 -
Study on a new type of digital coding track circuit
一種新型的數字編碼軌道電路 -
Coding equipments of track circuit in railway station
鐵路站內軌道電路電碼化設備 -
This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15
該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。 -
The whole correlation - inheritance coding circuit system is designed, simulated and verified in verilog hdl on the candence systems
採用了硬體描述語言verilog對整個相關繼承矢量量化圖像編碼電路系統在cadence系統上進行了西安理工大學碩士論文設計、模擬及時序驗證。 -
Finally, considering the advantages and disadvantages of these algorithms, a trade - off algorithm is proposed. a corresponding vlsi coding circuit system is designed and verified with fpga
最後結合各個演算法的優點，綜合考慮各方面性能，給出一個折衷的快速搜索演算法，並且設計出與演算法對應的編碼電路系統。 -
There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally
首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。 -
Secondly, we expatiate the work principle and the implemental method of ir wireless communication system and strongpoint and flaw of ir coding, then constitute the ir communication protocol which is used by both main body of charge station and appropriative remote device, design idiographic circuit of it
其次闡述了紅外無線通訊的原理、實現方法以及各種紅外編碼的優缺點;進而詳細制定了充電站主體和專用遙控器共同使用的紅外通訊協議，設計了具體的實現方法。 -
Based on a comprehensive research of image coding algorithm for correlation vq, novel algorithms are presented on two aspects in this paper, and corresponding vlsi coding circuit system is designed, simulated and verified
本論文在對相關矢量量化圖像編碼演算法進行深入分析的基礎上，在兩個方面提出了基於vlsi技術的新演算法，並進行了vlsi硬體設計、模擬模擬和時序驗證。 -
This paper describes the error control coding of the flex paging system, with emphasis on the design and implement of the flex decoder circuit by means of the fpga technology
本文介紹了flex高速無線尋呼系統中的差錯控制編碼技術，以及bch （ 32 ， 21 ）糾錯碼的構成和譯碼方法，重點討論了flex高速尋呼解碼晶元的fpga設計與實現。 -
The circuit design mainly includes interface designs, such as address coding circuit, memory, human - machine, ad converter, the power, etc. the pcb was protracted and tested
電路設計主要包括譯碼電路設計、存儲器介面電路設計、人機介面電路設計、 ad轉換器電路設計、數控恆流源介面設計等。 -
There ’ re two parts in the thesis : the design and implementation of fpga module and the design and implementation of the aes digital audio i / o circuit. i use xilinx corporation ’ s ise4. 2 as development tools to carry on fpga design, including hdl coding, functional simulation, logic synthesis, place & route and generation of programming files. fpga is used to implement audio routing, sine wave, adc ’ s calibration and led etc, . also, i have downloaded the configuration program into fpga chipset using mcu. eventually, the device is tested and the requirements of design is met
通過測試， etheraudio音頻路由器完全達到了設計要求。 etheraudio音頻路由器完全符合aes / ebu硬體規范，滿足專業音頻傳輸、路由需求。最後，本文還介紹了etheraudio音頻路由器在廣播電臺中的應用實例，通過分析該音頻路由器在廣播電臺的應用方式說明本課題的實際應用價值。 -
With performance of up to 900 million floating - point operations per second ( mflops ) at a clock rate of 150 mhz, tms320c6711 is fit to tackle with the problem. this thesis made a deep research on the h. 263 standard and the tms320c6711. we propose the plan of the software and the hardware for the realization of the h. 263 protocol which include the structure of the whole program, the c code of the key algorithm of the h. 263, the c code of some subprogram, and the circuit for image processing with the tms320c6711 as the processor. furthermore, we optimize some subprogram in common use to make the coding more quickly. we encode a video sequence with the tms320c6711dsk successfully, even if the compression rate is as high as 100, video effect we get after decoding the code stream is satisfying
首先系統地研究了h . 263協議編碼器的基本演算法，句法，碼流結構和tms320c6711dsk的原理結構以及ccs2 . 0的開發環境；在系統的軟體方面給出了總體流程圖，對于h . 263協議編碼器的某些核心演算法和子程序，給出了部分源代碼，對于dsp的各種代碼優化方法進行了討論，並且對代碼進行優化，從而在提高系統處理速度的同時減少代碼大小和內存需求量；硬體方面以tms320c6711為核心處理器，提出了基於tms320c6711的圖像處理平臺的硬體實現方案，並給出了原理電路圖；最後在tms320c6711dsk上成功對視頻數據進行高壓縮比（ 100倍以上）的編碼，對回傳的結果解碼后得到了令人滿意的效果。 -
In this paper, we briefly introduced the performance of wave coding and vocoder, emphasizedly studied the principle and performance of variable rate vocoder q4401, including the internal construction and pins, qcelp coder & vocoder, pcm interface, cpu interface initialization process, command format and so on. we also designed a application circuit, with the experiment validated its performance. in this design, the pcm interface chip is tp3057, it was used to finish a / d transform, the compress coding was finished by q4401, the initialization and control were accomplished by 8051 singlechip
重點是研究變速率語音編解碼晶元q4401的工作原理及性能。其中包括q4401的內部結構及管腳、 qcelp編碼方式、 pcm介面、 cpu介面、初始化過程、命令格式等，並在此基礎上，設計一個實際的應用電路，通過實驗，驗證其性能。在設計中用pcm介面晶元tp3057來完成從模擬信號到數字信號的轉換，再由q4401進行壓縮編碼，對q4401的初始化及控制由8051單片機來完成。
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