cpu architecture 中文意思是什麼

cpu architecture 解釋
中央處理機體系結構
  • cpu : CPU ＝ Central Processing Unit 【自動化】中央處理機。
  • architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
  1. Previous versions of embedded visual c allowed the selection of a cpu architecture that was not supported by the current active project

    Embedded visual c + +的早期版本允許選擇當前活動項目不支持的cpu結構。
  2. Because the common language runtime supplies a jit compiler for each supported cpu architecture, developers can write a set of msil that can be jit - compiled and run on computers with different architectures

    由於公共語言運行庫為所支持的每種cpu結構都提供了jit編譯器，開發人員可以編寫一組可在具有不同結構的計算機上進行jit編譯和運行的msil 。
  3. Different from general microprocessors, dsps have harvard architecture or enhanced harvard architecture and units of dsps can work in parallel. to perform multiplication in high speed, dsps also include hardware multiplier in its cpu

    與通用微處理器不同，數字信號處理器採用了哈佛總線結構或改進哈佛總線結構，具有高度的并行性，為了快速完成乘法計算在cpu中增設了硬體乘法單元。
  4. It includes chip selection, schematic circuit design, cpu selection and configuration, startup of the system, selection and configuration of embedded operation system, selection and configuration of tcp / ip software. it also describes some driver programming techniques of network controller. part 3 ( chapter 5 and 6 ) briefly introduces encryption technology and the ipsec protocol system, including architecture, mode, security association, security policy, implementation mode, processing of in / out packet, esp ( encapsulation security payload ), ah ( authentication header ), ike ( internet key exchange ) etc. the security requirements of embedded - networking is also analyzed

    本文首先探討了嵌入式網路的原理和設計要求，接著介紹了本文所開發的嵌入式系統的硬體平臺的設計（包括處理器的選擇與配置、存儲器的選擇和io設備的選用等） ，系統的啟動（包括bios和dos的啟動以及嵌入式操作系統vrtx的配置和引導） ，網路及其安全服務的實現（包括嵌入式協議棧usnet的選取、底層驅動程序的設計和安全協議ipsec的分析與實施） 。
  5. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too

    詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。
  6. Then the paper designed for cable modem frame by using a kind of top grade special cpu and an asic, when analyzing the hardware architecture, and finally formed the entire hardware system by integrating flash, dram, eprom, and e2prom memories, ethernet, rs232 interfaces, and high frequency circuit

    然後分析了硬體環境，論文中給出了利用一種高檔專用cpu和一塊超大規模asic為基礎設計出cablemodem的框圖。然後加上flash 、 dram 、 eprom 、 e2prom存儲器，以太網、 rs232介面，以及高頻頭電路，最後形成cablemodem的完整硬體系統。
  7. Traditional methods such as emulation can do little about it, it has to introduce some new arts. on the path of modern computer and cpu designing, the registers, level 1 cache, level 2 cache on the chip and level 3 cache on the mainboard, plus ram, hard disk or floppy disk or flash disk, make up of the modern multi - hiberarchy storage architecture

    現代計算機和cpu設計中， cpu片內的寄存器、一級高速緩存（ level1cache ）和二級高速緩存（ level2cache ） ，主板上的三級高速緩沖，再加上主存，外存（硬盤、軟盤、電子盤等） ，構成了現代計算機的多級存儲體系結構。
  8. Today, the risc architecture is the single most common cpu type in use and is the basis for everything from workstations to cell phones, video game consoles to supercomputers, traffic lights to desktops, and broadband modems to automobile fuel - injection and collision avoidance systems

    現在， risc體系結構是惟一一種最通用的cpu ，它是很多平臺的基礎：從工作站到蜂窩電話，從視頻游戲終端到超級計算機，從交通指示燈到桌面系統，從寬帶數據機到自動加油站和防撞系統。
  9. The ice of different embedded cpu can be completed in a piece of fpga. according to the architecture, a generic ice

    本模擬器的具體實現採用了altera公司的nios開發套件，自主研發出incircuit emulator知識產權
  10. Although gpu has a very high computing speed, algorithms implemented in cpu cannot be put to execute in gpu directly because of the discrepancy in instruction execution manner of the two. gpu ' s architecture is a high parallel simd instruction set system. to reimplement algorithms insufficient to run on cpu with programmable graphics hardware, it has to reconsider the data structures and procedures to implement them to make full use of the

    雖然gpu具有非常高的計算速度，但並不能將以前在cpu中實現的演算法直接放到gpu中來執行，這是因為gpu的指令執行方式和cpu不一樣， gpu的體系結構是一種高度并行的單指令多數據（ simd ）指令執行體系，所以要在可編程圖形硬體上實現在cpu中效率不高的演算法，就需要重新制定演算法實現的數據結構和步驟，以充分利用gpu并行處理體系結構帶來的性能優勢。
  11. The architecture allows only as many concurrently executing requests as there is cpu power available

    該結構將根據可用於請求的cpu功率，來決定允許同時執行的請求數。
  12. In other words, the intel - based architecture describes much more than just the cpu

    換句話說，以英代爾為主的結構描述比只是處理器多許多。
  13. The target architecture of hardware - software combined design consists of a cpu and some asic communicating over a bus

    摘要軟硬體協同設計的目標結構包括一個cpu和多個asic ，它們通過一條總線進行通信。
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